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* vhdl-sem_assocs: improve error messageTristan Gingold2022-08-251-1/+1
* synth: handle component aspect configurationTristan Gingold2022-08-251-1/+5
* simul: handle connections of recordsTristan Gingold2022-08-251-1/+18
* synth: handle indexes/ranges in configurations for generate blocksTristan Gingold2022-08-252-5/+30
* synth: handle unbounded top-level portsTristan Gingold2022-08-251-9/+18
* synth: handle type left/right attributesTristan Gingold2022-08-253-0/+26
* simul: improve support of float signalsTristan Gingold2022-08-241-3/+7
* grt-disp_signals: also disp conversions rangesTristan Gingold2022-08-241-0/+11
* simul: handle conversions and associations with constantsTristan Gingold2022-08-242-70/+399
* simul: simplify codeTristan Gingold2022-08-232-16/+7
* simul: factorize code to compute number of sourcesTristan Gingold2022-08-234-120/+50
* simul-vhdl_debug: disp nbr sourcesTristan Gingold2022-08-231-1/+15
* simul: add extra drivers for ports without sourcesTristan Gingold2022-08-233-14/+152
* elab: add default value to portsTristan Gingold2022-08-234-13/+28
* grt-signals: add ghdl_signal_add_extra_driverTristan Gingold2022-08-232-0/+19
* grt-signals: internal refactoring for drivers creationTristan Gingold2022-08-221-25/+39
* synth-vhdl_static_proc: handle std.env.finishTristan Gingold2022-08-211-1/+2
* simul-vhdl_simul: handle waveforms in signal assignmentsTristan Gingold2022-08-212-40/+51
* synth: factorize code for synth_subtype_conversionTristan Gingold2022-08-219-53/+35
* grt-errors: remove error_hook (was unused)Tristan Gingold2022-08-212-14/+0
* simul: rework assertions execution and error handlingTristan Gingold2022-08-215-10/+13
* simul: handle concurrent procedure calls (WIP)Tristan Gingold2022-08-211-15/+95
* simul: handle after clauses in signal assignmentTristan Gingold2022-08-213-70/+111
* simul-vhdl_simul: add support for PSL directivesTristan Gingold2022-08-204-34/+289
* elab-vhdl_expr: factorize codeTristan Gingold2022-08-1910-998/+50
* simul-vhdl_debug: display connectionsTristan Gingold2022-08-191-5/+63
* simul: handle resolved signals (WIP)Tristan Gingold2022-08-194-49/+332
* ghdlsimul: add an option to debug before elaborationTristan Gingold2022-08-183-3/+6
* simul: handle individual associationsTristan Gingold2022-08-172-4/+16
* simul: add create_connectsTristan Gingold2022-08-174-46/+144
* simul: create terminals (WIP)Tristan Gingold2022-08-174-8/+62
* elab-vhdl_objtypes: handle holes in comparisons.Tristan Gingold2022-08-161-7/+72
* netlists-memories: add a TODO commentTristan Gingold2022-08-161-0/+8
* synth/netlists: add commentsTristan Gingold2022-08-162-7/+14
* synth-vhdl_expr: optimize record with one element.Tristan Gingold2022-08-161-3/+3
* netlists-memories: renaming and add commentsTristan Gingold2022-08-161-25/+38
* psl-rewrites: minor style changeTristan Gingold2022-08-161-2/+1
* vhdl-prints: improve handling of PSL. For #2178Tristan Gingold2022-08-156-63/+184
* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-1513-226/+292
* elab-vhdl_values-debug: improve output of debug_valtypTristan Gingold2022-08-141-1/+3
* synth-vhdl_context: fix handling of alias in get_net. Fix #2177Tristan Gingold2022-08-141-4/+3
* vhdl: recognize log10 and sqrt from math_real. Fix #2176Tristan Gingold2022-08-144-10/+32
* synth: handle assignment to record aggregateTristan Gingold2022-08-142-31/+109
* netlists-memories: improve checks to avoid the crash of #2077Tristan Gingold2022-08-141-32/+75
* netlists-memories: fix a crash on multi-dim memories. For #2077Tristan Gingold2022-08-131-3/+6
* trans-chap3: fix invalid copy of element layout. For #2166Tristan Gingold2022-08-121-2/+4
* vhdl: add support for file subtype. Fix #2174Tristan Gingold2022-08-1112-262/+329
* vhdl-sem_stmts: handle external signal names in force assign. Fix #2173Tristan Gingold2022-08-111-1/+5
* vhdl-parse.adb: parse pathname expressionTristan Gingold2022-08-111-0/+10
* vhdl-sem_stmts.adb: handle signal assignment to external names. Fix #2172Tristan Gingold2022-08-111-0/+4
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