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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-17 09:25:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-17 09:25:47 +0200 |
| commit | 89704a2dd494956c8686b7d483d8847262ca2a3d (patch) | |
| tree | 427f0fc4a4c1d004a224a8d065ba60ea78a2dd5c /src | |
| parent | a546ecfe5c8643c72435318de3973cbf83993fa4 (diff) | |
| download | ghdl-89704a2dd494956c8686b7d483d8847262ca2a3d.tar.gz ghdl-89704a2dd494956c8686b7d483d8847262ca2a3d.tar.bz2 ghdl-89704a2dd494956c8686b7d483d8847262ca2a3d.zip | |
simul: handle individual associations
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 9 | ||||
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 11 |
2 files changed, 16 insertions, 4 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 9539645e3..33501a536 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -358,6 +358,7 @@ package body Simul.Vhdl_Elab is Assoc_Inter : Node; Assoc : Node; Inter : Node; + Formal : Node; Formal_Base : Valtyp; Actual_Base : Valtyp; Formal_Sig : Signal_Index_Type; @@ -375,11 +376,16 @@ package body Simul.Vhdl_Elab is case Get_Kind (Assoc) is when Iir_Kind_Association_Element_By_Name => Inter := Get_Association_Interface (Assoc, Assoc_Inter); + Formal := Get_Formal (Assoc); + if Formal = Null_Iir then + Formal := Inter; + end if; Synth_Assignment_Prefix - (Port_Inst, Inter, Formal_Base, Typ, Off, Dyn); + (Port_Inst, Formal, Formal_Base, Typ, Off, Dyn); pragma Assert (Dyn = No_Dyn_Name); Formal_Sig := Formal_Base.Val.S; Formal_Ep := (Formal_Sig, Off, Typ); + Synth_Assignment_Prefix (Assoc_Inst, Get_Actual (Assoc), Actual_Base, Typ, Off, Dyn); pragma Assert (Dyn = No_Dyn_Name); @@ -416,7 +422,6 @@ package body Simul.Vhdl_Elab is raise Internal_Error; end case; - Connect_Table.Append (Conn); Signals_Table.Table (Formal_Sig).Connect := Connect_Table.Last; diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 70fdc86cb..b44028c57 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -1618,7 +1618,8 @@ package body Simul.Vhdl_Simul is end; return; when Type_Logic - | Type_Bit => + | Type_Bit + | Type_Discrete => declare S, D : Ghdl_Signal_Ptr; begin @@ -1669,7 +1670,13 @@ package body Simul.Vhdl_Simul is C : Connect_Entry renames Connect_Table.Table (I); begin if not C.Collapsed then - Create_Connect (C); + if C.Actual.Base /= No_Signal_Index then + Create_Connect (C); + elsif Get_Expr_Staticness (Get_Actual (C.Assoc)) >= Globally + then + -- TODO: association with static expr. + raise Internal_Error; + end if; end if; end; end loop; |