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* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-4/+0
* vhdl-utils(free_recursive): only free the name (not the entity)Tristan Gingold2021-07-221-1/+1
* adjust previous commit (no identifier in Psl_Default_Clock)Tristan Gingold2021-07-011-0/+1
* vhdl-utils: element attribute is a type markTristan Gingold2021-05-251-1/+2
* vhdl-utils: an object alias may not have a subtype indication. Fix #1765Tristan Gingold2021-05-161-5/+10
* vhdl and libraries: add support for binding to a foreign moduleTristan Gingold2021-04-051-4/+9
* vhdl: add Iir_Kind_Foreign_ModuleTristan Gingold2021-04-051-0/+8
* Add base support for the attribue element in vhdl 08Anselmo952021-04-031-0/+6
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-0/+2
* update license headersumarcor2021-01-141-11/+9
* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-0/+9
* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-0/+2
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-13/+36
* vhdl: improve support of subtype attribute.Tristan Gingold2020-07-181-0/+53
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-68/+72
* vhdl-utils: factorize Get_File_Signature.Tristan Gingold2020-05-151-0/+101
* trans-chap7: Translate_Equality: also convert to base type for records.Tristan Gingold2020-05-131-0/+11
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-7/+7
* vhdl-prints: handle evaluated expression for qualified_expression.Tristan Gingold2020-04-181-0/+28
* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-4/+2
* Fix regressions after previous commit.Tristan Gingold2020-03-011-0/+5
* vhdl: a function call is not an object. Fix #1138.Tristan Gingold2020-03-011-14/+23
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-0/+30
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-24/+83
* synth: improve support of arrays or arrays. Fix #955Tristan Gingold2019-10-011-13/+8
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-0/+1
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-101-0/+16
* synth: minor rework.Tristan Gingold2019-07-221-0/+10
* vhdl: cleanup in clear_instantiation_configuration.Tristan Gingold2019-07-131-66/+19
* vhdl: minor reformating.Tristan Gingold2019-07-111-5/+2
* vhdl: translate anonymous_signal_declaration.Tristan Gingold2019-07-031-1/+3
* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-031-1/+4
* vhdl: move Current_Text from vhdl-utils to vhdl-parse.Tristan Gingold2019-05-251-24/+3
* vhdl-utils: avoid a crash on architecture without name.Tristan Gingold2019-05-211-0/+2
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-1/+1
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-0/+1688