aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl/vhdl-parse.adb
Commit message (Expand)AuthorAgeFilesLines
* vhdl: --std93c is now an alias for --std=93 -frelaxedTristan Gingold2020-06-131-3/+5
* vhdl-parse: always keep parentheses in case expression. For #1364Tristan Gingold2020-06-131-3/+18
* vhdl: parse statements in verification units.Tristan Gingold2020-06-111-91/+96
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-4/+63
* vhdl: avoid crash on incorrect type mark in subtype indication.Tristan Gingold2020-04-271-9/+17
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-2/+2
* vhdl-parse: avoid resync_to_end_of_statement.Tristan Gingold2020-03-061-0/+2
* vhdl-parse: avoid error cascade for 'subtype before 08.Tristan Gingold2020-03-011-1/+0
* vhdl-parse: improve error messages and recovery.Tristan Gingold2020-02-271-8/+46
* vhdl-parse: improve recovery for incorrect end identifier.Tristan Gingold2020-02-131-8/+27
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-24/+130
* ams-vhdl: handle record nature end name.Tristan Gingold2019-12-301-0/+3
* ams-vhdl: improve error recoveryTristan Gingold2019-12-301-1/+2
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-206/+1069
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-2/+13
* vhdl: extract sem_concurrent_statement, to handle hdl stmt in vunits.Tristan Gingold2019-10-251-26/+25
* vhdl-parse: do not scan PSL keywords in vunit declarations.Tristan Gingold2019-10-241-0/+4
* vhdl-sem_decls: make sem_declaration public.Tristan Gingold2019-10-231-0/+2
* vhdl-parse: parse declarations in vunit.Tristan Gingold2019-10-211-327/+352
* vhdl: handle labels in verification units.Tristan Gingold2019-10-211-8/+62
* vhdl: check cover/restrict is followed by a sequence.Tristan Gingold2019-10-161-2/+2
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-151-0/+4
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-4/+4
* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-1/+11
* vhdl: handle assume in verification units.Tristan Gingold2019-08-201-0/+3
* synth: handle verification units.Tristan Gingold2019-08-201-0/+1
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-67/+134
* vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.Tristan Gingold2019-08-141-0/+9
* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-141-37/+33
* vhdl: avoid crash on incorrect unit name.Tristan Gingold2019-08-101-2/+22
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-101-0/+3
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-4/+26
* vhdl: allow discrete subtype indication for discrete_range.Tristan Gingold2019-08-061-0/+3
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-1/+1
* parse: improve error message for incorrect use of '!'.Tristan Gingold2019-07-041-0/+4
* vhdl: parse and analyze restrict directive.Tristan Gingold2019-07-041-3/+25
* vhdl-parse: improve error message in case of unexpectedTristan Gingold2019-06-131-0/+12
* vhdl-disp_vhdl: print literals and identifiers from the source.Tristan Gingold2019-05-291-6/+14
* vhdl: move Current_Text from vhdl-utils to vhdl-parse.Tristan Gingold2019-05-251-0/+20
* vhdl: update AMS parsing.Tristan Gingold2019-05-241-1/+15
* vhdl-parse: Add Has_Is for block_statement.Tristan Gingold2019-05-241-0/+2
* vhdl-parse: minor changes for disp_vhdl.Tristan Gingold2019-05-241-0/+5
* vhdl: add hook on free_node, automatically freeTristan Gingold2019-05-221-3/+0
* vhdl-parse: strenghten.Tristan Gingold2019-05-151-9/+13
* errorout: add messages group instead of continuation.Tristan Gingold2019-05-121-24/+27
* vhdl-parse: improve error messages. Fix #818Tristan Gingold2019-05-111-0/+14
* vhdl: decouple errorouts a bit more.Tristan Gingold2019-05-101-3/+5
* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-101-3/+3
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 16:04:44 +0000