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* vhdl-parse: support for-generate in vunits. Fix #1850Tristan Gingold2021-08-271-2/+10
* vhdl-parse.adb: improve error recovery. For #1837Tristan Gingold2021-08-241-0/+2
* vhdl-parse: use if_generate_else_clause for elsif clauses. Fix #1824Tristan Gingold2021-07-291-1/+1
* vhdl: move check on instantiation name from sem to parse.Tristan Gingold2021-07-281-0/+3
* vhdl: avoid a crash on forced analysis of a erroneous name expressionTristan Gingold2021-05-281-20/+17
* src: Clarify error for conditional signal assignment.Ondrej Ille2021-04-111-1/+2
* src: Allow case generate only in VHDL 2008.Ondrej Ille2021-04-111-0/+1
* src: Unify check for VHDL at least 2008Ondrej Ille2021-04-111-47/+25
* src: Remove obsolete FIXME, file_open_information parsed. Default "IN"/"READ_...Ondrej Ille2021-04-051-1/+0
* src: Better reporting of missing parenthesis.Ondrej Ille2021-04-031-5/+24
* src: Add Resync_To_End_Of_External_Name.Ondrej Ille2021-04-031-1/+21
* vhdl-parse.adb: fix indentation (for #1711)Tristan Gingold2021-04-031-30/+31
* src: More detailed message on invalid variable locations.Ondrej Ille2021-04-031-12/+46
* src: Provide nicer message if Tok_Is is swapped with Tok_Assign for alias.Ondrej Ille2021-04-031-2/+6
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-0/+6
* update license headersumarcor2021-01-141-11/+9
* vhdl-parse.adb: improve diagnostic messagesTristan Gingold2021-01-051-1/+2
* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-051-0/+2
* vhdl-parse: improve error recovery on extra right parenthesisTristan Gingold2020-11-041-7/+21
* vhdl-parse: improve error recovery on tick.Tristan Gingold2020-11-041-0/+5
* vhdl-parse: do not skip token in case of error. Fix #1500Tristan Gingold2020-10-291-1/+1
* vhdl-parse: improve error message for extra '('.Tristan Gingold2020-10-091-1/+5
* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-86/+174
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-11/+110
* vhdl: --std93c is now an alias for --std=93 -frelaxedTristan Gingold2020-06-131-3/+5
* vhdl-parse: always keep parentheses in case expression. For #1364Tristan Gingold2020-06-131-3/+18
* vhdl: parse statements in verification units.Tristan Gingold2020-06-111-91/+96
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-4/+63
* vhdl: avoid crash on incorrect type mark in subtype indication.Tristan Gingold2020-04-271-9/+17
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-2/+2
* vhdl-parse: avoid resync_to_end_of_statement.Tristan Gingold2020-03-061-0/+2
* vhdl-parse: avoid error cascade for 'subtype before 08.Tristan Gingold2020-03-011-1/+0
* vhdl-parse: improve error messages and recovery.Tristan Gingold2020-02-271-8/+46
* vhdl-parse: improve recovery for incorrect end identifier.Tristan Gingold2020-02-131-8/+27
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-24/+130
* ams-vhdl: handle record nature end name.Tristan Gingold2019-12-301-0/+3
* ams-vhdl: improve error recoveryTristan Gingold2019-12-301-1/+2
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-206/+1069
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-2/+13
* vhdl: extract sem_concurrent_statement, to handle hdl stmt in vunits.Tristan Gingold2019-10-251-26/+25
* vhdl-parse: do not scan PSL keywords in vunit declarations.Tristan Gingold2019-10-241-0/+4
* vhdl-sem_decls: make sem_declaration public.Tristan Gingold2019-10-231-0/+2
* vhdl-parse: parse declarations in vunit.Tristan Gingold2019-10-211-327/+352
* vhdl: handle labels in verification units.Tristan Gingold2019-10-211-8/+62
* vhdl: check cover/restrict is followed by a sequence.Tristan Gingold2019-10-161-2/+2
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-151-0/+4
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-4/+4
* vhdl: handle architecture in verification unit hierarchical name.Tristan Gingold2019-08-201-1/+11
* vhdl: handle assume in verification units.Tristan Gingold2019-08-201-0/+3
* synth: handle verification units.Tristan Gingold2019-08-201-0/+1
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