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* vhdl-nodes: reorder, add iir_kinds_structural_statementTristan Gingold2022-04-291-9/+17
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* synth: add support for subtype declaration in vunits. Fix #2033Tristan Gingold2022-04-131-0/+2
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* synth: do not add info for element subtype (except for arrays).Tristan Gingold2022-04-051-0/+1
| | | | Fix #2021
* vhdl: parse return identifier (v19)Tristan Gingold2022-03-041-0/+7
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* vhdl: recognize ror/rol from ieee.numeric_std. For #1909Tristan Gingold2021-11-111-0/+4
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* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-29/+30
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-041-6/+16
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* vhdl: also warns on unused enumeration literalTristan Gingold2021-11-011-0/+2
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* Add parsing of case? statement and simple test.Brian Padalino2021-09-241-0/+7
| | | | Also add the Matching flag to the Iir_Kind_Case_Statement.
* trans-chap9.adb: handle async_abort, sync_abort. Fix #1654Tristan Gingold2021-08-301-0/+16
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* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-0/+7
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* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-26/+0
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* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-0/+11
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* vhdl-sem_expr.adb: build element subtype for aggregate when possible.Tristan Gingold2021-08-031-2/+2
| | | | | | | | In case of array aggregate whose element subtype is not bounded, extract it from the aggregate elements. Fix #1055 Fix #1455
* adjust previous commit (no identifier in Psl_Default_Clock)Tristan Gingold2021-07-011-2/+1
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* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-301-3/+0
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* vhdl: handle mod/rem for physical. Fix #1810Tristan Gingold2021-06-301-0/+2
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* vhdl-nodes: do not reset free hooks on initializationTristan Gingold2021-06-261-0/+2
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* vhdl-nodes.ads: use pnodes layout for Number_Base_TypeTristan Gingold2021-06-181-1/+8
| | | | So that it can be extracted.
* vhdl: remove unused Get/Set_Alias_DeclarationTristan Gingold2021-05-161-14/+0
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* vhdl: add Iir_Kind_Foreign_ModuleTristan Gingold2021-04-051-0/+31
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* synth: handle pow and arctan from ieee.math_real. Fix #1665Tristan Gingold2021-02-271-0/+2
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* vhdl-nodes.ads: add a commentTristan Gingold2021-02-271-0/+2
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* vhdl-nodes.ads: reorder fields of block_configuration to match grammarTristan Gingold2021-02-201-6/+6
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* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-1/+14
| | | | | | | | | | | | | | | * vhdl: parse PSL onehot/onehot0 builtin calls. For #662 * update pyGHDL bindings * Synthesis of PSL built-in onehot/onehot0 function. * testsuite/synth: add tests of PSL built-in functions onehot()/onehot0() for #662 * doc: add info about PSL built-in functions onehot()/onehot0() for #662 * synth: refactor synthesis of onehot/onehot0 functions Co-authored-by: eine <eine@users.noreply.github.com>
* vhdl: recognize to_stdlogicvector. For #1628Tristan Gingold2021-02-041-0/+1
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* update license headersumarcor2021-01-141-11/+9
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* Typo fixes in Ada code.Patrick Lehmann2021-01-101-45/+45
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* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-051-0/+17
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* vhdl: recognize ieee.numeric_std_unsigned. For #1572Tristan Gingold2021-01-011-0/+3
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* Rework initialization and finalization.Tristan Gingold2020-12-301-1/+4
| | | | libghdl can now be re-initialized.
* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-081-0/+12
| | | | | | | | | | | | | Attributes of entity/architecture/configurations are expected to be locally static so that they can be referenced from outside (so on the non-instantiated entity). But many designs break this assumption. In relaxed mode, non-locally static attributes are allowed but now cannot be referenced outside the entity. Locally static attributes can be referenced from outside. Fix #1528
* vhdl: recognize logica vec/log and log/vec operators. For #1520Tristan Gingold2020-12-031-0/+14
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* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-2/+8
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* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-0/+30
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* vhdl: recognize find_leftmost/find_rightmost. For #1460Tristan Gingold2020-09-161-0/+6
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* vhdl: recognize reduce operations from numeric_std.Tristan Gingold2020-09-141-0/+14
| | | | Handle them in synthesis.
* vhdl: recognize more operators for std_logic_unsigned/signed.Tristan Gingold2020-08-071-0/+36
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* vhdl: recognize more std_logic_arith operators.Tristan Gingold2020-08-071-0/+15
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* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+44
| | | | For #1416
* vhdl: adjust hanlding of guard signals for translate.Tristan Gingold2020-07-251-0/+2
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* translate: improve support of unbounded records and arrays.Tristan Gingold2020-07-251-0/+3
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* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-38/+13
| | | | | Only for subtype definition and remove base_type in type definitions. Allows to better track the addition of contraints.
* vhdl: fix ownership for recors subtypes.Tristan Gingold2020-07-181-3/+7
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* vhdl-nodes: reduce size of Iterator_Declaration.Tristan Gingold2020-07-011-3/+3
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* vhdl-nodes: make Subtype_Indication Maybe_Ref. For #641Tristan Gingold2020-06-301-3/+14
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* vhdl-nodes: add Open_Flag to all generic interfaces.Tristan Gingold2020-06-261-3/+10
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* synth: handle std_logic_signed.conv_integer. For ghdl/ghdl-yosys-plugin#126Tristan Gingold2020-06-191-0/+2
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* vhdl: decode to_x01 (from ieee.std_logic_1164)Tristan Gingold2020-06-191-0/+21
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* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-4/+10
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