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* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-111-1/+6
* vhdl: recognize mod/rem operators.Tristan Gingold2020-03-101-0/+14
* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-0/+9
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-181-0/+6
* synth: handle some rotation and shifts. Fix #1077Tristan Gingold2020-01-301-0/+5
* synth: handle matching comparisons. Fix #1109Tristan Gingold2020-01-241-0/+42
* synth: add id_abs gate. For #1101Tristan Gingold2020-01-201-0/+2
* synth: handle more signed operations. For #1101Tristan Gingold2020-01-191-0/+4
* vhdl: recognize predefined shift operators for ieee.numeric_std. For #1077Tristan Gingold2020-01-111-0/+9
* synth: handle ieee.math_real.round Fix #1075Tristan Gingold2020-01-101-0/+1
* ams-vhdl: add support for 'delayed for quantity.Tristan Gingold2019-12-311-0/+4
* ams-vhdl: handle zoh, ltf and ztf attributes.Tristan Gingold2019-12-311-0/+25
* ams-vhdl: add simultaneous null statement.Tristan Gingold2019-12-301-0/+39
* ams-vhdl: add frequency function, minor fixes.Tristan Gingold2019-12-301-0/+1
* ams-vhdl: improve error recoveryTristan Gingold2019-12-301-0/+1
* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-301-2/+7
* ams-vhdl: fix tree consistency for terminal declaration.Tristan Gingold2019-12-301-2/+2
* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-301-1/+15
* vhdl-ams: fix tree consistency for subnature declaration.Tristan Gingold2019-12-291-4/+4
* vhdl-ams: fix overload for simple simultaneous statement.Tristan Gingold2019-12-291-0/+4
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-28/+643
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-261-0/+11
* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-241-0/+3
* vhdl: recognize sin and cos from math_real.Tristan Gingold2019-11-261-0/+2
* synth: preliminary work to support intrinsic procedures.Tristan Gingold2019-11-141-0/+5
* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-061-0/+3
* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-301-0/+2
* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-131-0/+2
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-111-1/+6
* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-111-0/+13
* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-111-0/+6
* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-101-1/+7
* synth: handle package bodies.Tristan Gingold2019-10-071-0/+1
* vhdl: recognize to_bitvector.Tristan Gingold2019-10-071-0/+2
* vhdl: recognize div operators.Tristan Gingold2019-09-301-0/+7
* vhdl: recognize rotate functions.Tristan Gingold2019-09-221-0/+5
* vhdl: add exit/next flags.Tristan Gingold2019-09-181-0/+22
* vhdl-nodes: add a comment.Tristan Gingold2019-09-121-1/+1
* vhdl: recognize numeric_std shift_left.Tristan Gingold2019-09-111-0/+5
* vhdl: recognize numeric_std mul.Tristan Gingold2019-09-071-0/+7
* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-021-3/+4
* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-021-0/+4
* vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-301-0/+7
* vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-301-0/+2
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-201-0/+4
* synth: handle verification units.Tristan Gingold2019-08-201-1/+13
* vhdl: parse verification unit (WIP).Tristan Gingold2019-08-171-23/+30
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-6/+58
* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-151-0/+21
* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-111-0/+4
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