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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-06 08:02:37 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-06 08:02:37 +0100 |
| commit | c6023180ffa061cf4394633642763b7d3546c737 (patch) | |
| tree | 6fdc9087b71fcaca2c57d38de83b83eafbf6b151 /src/vhdl/vhdl-nodes.ads | |
| parent | 3819515f724ed2ae81a1aa7b467359e26a3fb9e7 (diff) | |
| download | ghdl-c6023180ffa061cf4394633642763b7d3546c737.tar.gz ghdl-c6023180ffa061cf4394633642763b7d3546c737.tar.bz2 ghdl-c6023180ffa061cf4394633642763b7d3546c737.zip | |
vhdl: recognize rising_edge/falling_edge.
Diffstat (limited to 'src/vhdl/vhdl-nodes.ads')
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index d02cddbc9..57b0675ff 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4915,6 +4915,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_To_Bitvector, + Iir_Predefined_Ieee_1164_Rising_Edge, + Iir_Predefined_Ieee_1164_Falling_Edge, + -- VHDL-2008 unary logic operators Iir_Predefined_Ieee_1164_Vector_And_Reduce, Iir_Predefined_Ieee_1164_Vector_Or_Reduce, |