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* vhdl-sem_assocs: handle association with external signal names.Tristan Gingold2022-10-181-0/+3
| | | | Fix #2221
* simul: add support for protected objectsTristan Gingold2022-09-081-1/+1
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* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-151-3/+23
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* vhdl: add support for file subtype. Fix #2174Tristan Gingold2022-08-111-0/+21
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* vhdl: add Determined_Aggregate_Flag field. For #2166Tristan Gingold2022-08-101-0/+7
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* vhdl: add an owner to interface type definitionTristan Gingold2022-08-071-0/+7
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* vhdl: add support for default in interface subprogram. Fix #2163Tristan Gingold2022-08-071-0/+14
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* vhdl-nodes: add Get/Set_Stop_Flag. For #2150Tristan Gingold2022-07-291-0/+8
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* vhdl-nodes: add Get/Set_Reference_Terminal_FlagTristan Gingold2022-07-251-0/+10
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* vhdl-nodes: renaming.Tristan Gingold2022-07-211-13/+13
| | | | | | | Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities.
* vhdl: add Iir_Kinds_AMS_Signal_AttributeTristan Gingold2022-07-161-2/+10
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* vhdl: avoid crash on incorrect use of signaturesTristan Gingold2022-07-021-0/+4
| | | | For #2116
* vhdl: add a parent field to protected_type_declaration. Fix #2091Tristan Gingold2022-06-121-0/+3
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* vhdl-nodes: add Inertial_Flag for association_element_by_expressionTristan Gingold2022-06-121-0/+9
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* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-111-2/+2
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* vhdl-ieee-math_real: recognize more operationsTristan Gingold2022-06-061-1/+19
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* synth-vhdl_eval: recognize and handle to_stdulogicvectorTristan Gingold2022-06-061-0/+7
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* vhdl: recognize more predefined ieee functions and operatorsTristan Gingold2022-06-051-1/+40
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* vhdl-ieee-numeric: recognize vector/scalar operationsTristan Gingold2022-06-051-3/+27
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* vhdl-ieee-numeric: recognize is_x, to_x01, to_ux01 and to_x01zTristan Gingold2022-06-051-0/+12
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* vhdl-ieee-std_logic_1164: recognize to_hstring, to_ostringTristan Gingold2022-06-011-0/+3
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* vhdl: recognize numeric_bit.to_unsignedTristan Gingold2022-05-311-0/+10
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* vhdl-nodes: move maximum/minimum out of predefined operator rangeTristan Gingold2022-05-301-27/+27
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-05-291-5/+8
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* vhdl: recognize subprograms from std.envTristan Gingold2022-05-291-0/+7
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* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-1/+40
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* vhdl-nodes: remove unused fields for procedure declarationsTristan Gingold2022-05-171-0/+2
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* vhdl: add suspend state pseudo decl and stmt. WIP.Tristan Gingold2022-05-171-0/+19
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* vhdl-nodes: reorder, add iir_kinds_structural_statementTristan Gingold2022-04-291-9/+17
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* synth: add support for subtype declaration in vunits. Fix #2033Tristan Gingold2022-04-131-0/+2
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* synth: do not add info for element subtype (except for arrays).Tristan Gingold2022-04-051-0/+1
| | | | Fix #2021
* vhdl: parse return identifier (v19)Tristan Gingold2022-03-041-0/+7
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* vhdl: recognize ror/rol from ieee.numeric_std. For #1909Tristan Gingold2021-11-111-0/+4
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* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-29/+30
| | | | | (instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-041-6/+16
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* vhdl: also warns on unused enumeration literalTristan Gingold2021-11-011-0/+2
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* Add parsing of case? statement and simple test.Brian Padalino2021-09-241-0/+7
| | | | Also add the Matching flag to the Iir_Kind_Case_Statement.
* trans-chap9.adb: handle async_abort, sync_abort. Fix #1654Tristan Gingold2021-08-301-0/+16
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* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-0/+7
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* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-26/+0
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* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-0/+11
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* vhdl-sem_expr.adb: build element subtype for aggregate when possible.Tristan Gingold2021-08-031-2/+2
| | | | | | | | In case of array aggregate whose element subtype is not bounded, extract it from the aggregate elements. Fix #1055 Fix #1455
* adjust previous commit (no identifier in Psl_Default_Clock)Tristan Gingold2021-07-011-2/+1
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* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-301-3/+0
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* vhdl: handle mod/rem for physical. Fix #1810Tristan Gingold2021-06-301-0/+2
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* vhdl-nodes: do not reset free hooks on initializationTristan Gingold2021-06-261-0/+2
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* vhdl-nodes.ads: use pnodes layout for Number_Base_TypeTristan Gingold2021-06-181-1/+8
| | | | So that it can be extracted.
* vhdl: remove unused Get/Set_Alias_DeclarationTristan Gingold2021-05-161-14/+0
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* vhdl: add Iir_Kind_Foreign_ModuleTristan Gingold2021-04-051-0/+31
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* synth: handle pow and arctan from ieee.math_real. Fix #1665Tristan Gingold2021-02-271-0/+2
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