| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | vhdl-sem_assocs: handle association with external signal names. | Tristan Gingold | 2022-10-18 | 1 | -0/+3 |
| * | simul: add support for protected objects | Tristan Gingold | 2022-09-08 | 1 | -1/+1 |
| * | vhdl: add iir_kind_psl_boolean_parameter node. For #2178 | Tristan Gingold | 2022-08-15 | 1 | -3/+23 |
| * | vhdl: add support for file subtype. Fix #2174 | Tristan Gingold | 2022-08-11 | 1 | -0/+21 |
| * | vhdl: add Determined_Aggregate_Flag field. For #2166 | Tristan Gingold | 2022-08-10 | 1 | -0/+7 |
| * | vhdl: add an owner to interface type definition | Tristan Gingold | 2022-08-07 | 1 | -0/+7 |
| * | vhdl: add support for default in interface subprogram. Fix #2163 | Tristan Gingold | 2022-08-07 | 1 | -0/+14 |
| * | vhdl-nodes: add Get/Set_Stop_Flag. For #2150 | Tristan Gingold | 2022-07-29 | 1 | -0/+8 |
| * | vhdl-nodes: add Get/Set_Reference_Terminal_Flag | Tristan Gingold | 2022-07-25 | 1 | -0/+10 |
| * | vhdl-nodes: renaming. | Tristan Gingold | 2022-07-21 | 1 | -13/+13 |
| * | vhdl: add Iir_Kinds_AMS_Signal_Attribute | Tristan Gingold | 2022-07-16 | 1 | -2/+10 |
| * | vhdl: avoid crash on incorrect use of signatures | Tristan Gingold | 2022-07-02 | 1 | -0/+4 |
| * | vhdl: add a parent field to protected_type_declaration. Fix #2091 | Tristan Gingold | 2022-06-12 | 1 | -0/+3 |
| * | vhdl-nodes: add Inertial_Flag for association_element_by_expression | Tristan Gingold | 2022-06-12 | 1 | -0/+9 |
| * | vhdl: recognize ieee.math_real.sign, fix is_x recogn. | Tristan Gingold | 2022-06-11 | 1 | -2/+2 |
| * | vhdl-ieee-math_real: recognize more operations | Tristan Gingold | 2022-06-06 | 1 | -1/+19 |
| * | synth-vhdl_eval: recognize and handle to_stdulogicvector | Tristan Gingold | 2022-06-06 | 1 | -0/+7 |
| * | vhdl: recognize more predefined ieee functions and operators | Tristan Gingold | 2022-06-05 | 1 | -1/+40 |
| * | vhdl-ieee-numeric: recognize vector/scalar operations | Tristan Gingold | 2022-06-05 | 1 | -3/+27 |
| * | vhdl-ieee-numeric: recognize is_x, to_x01, to_ux01 and to_x01z | Tristan Gingold | 2022-06-05 | 1 | -0/+12 |
| * | vhdl-ieee-std_logic_1164: recognize to_hstring, to_ostring | Tristan Gingold | 2022-06-01 | 1 | -0/+3 |
| * | vhdl: recognize numeric_bit.to_unsigned | Tristan Gingold | 2022-05-31 | 1 | -0/+10 |
| * | vhdl-nodes: move maximum/minimum out of predefined operator range | Tristan Gingold | 2022-05-30 | 1 | -27/+27 |
| * | synth-vhdl_eval: handle more operations | Tristan Gingold | 2022-05-29 | 1 | -5/+8 |
| * | vhdl: recognize subprograms from std.env | Tristan Gingold | 2022-05-29 | 1 | -0/+7 |
| * | vhdl-canon: add Canon_Add_Suspend_State | Tristan Gingold | 2022-05-26 | 1 | -1/+40 |
| * | vhdl-nodes: remove unused fields for procedure declarations | Tristan Gingold | 2022-05-17 | 1 | -0/+2 |
| * | vhdl: add suspend state pseudo decl and stmt. WIP. | Tristan Gingold | 2022-05-17 | 1 | -0/+19 |
| * | vhdl-nodes: reorder, add iir_kinds_structural_statement | Tristan Gingold | 2022-04-29 | 1 | -9/+17 |
| * | synth: add support for subtype declaration in vunits. Fix #2033 | Tristan Gingold | 2022-04-13 | 1 | -0/+2 |
| * | synth: do not add info for element subtype (except for arrays). | Tristan Gingold | 2022-04-05 | 1 | -0/+1 |
| * | vhdl: parse return identifier (v19) | Tristan Gingold | 2022-03-04 | 1 | -0/+7 |
| * | vhdl: recognize ror/rol from ieee.numeric_std. For #1909 | Tristan Gingold | 2021-11-11 | 1 | -0/+4 |
| * | vhdl: Iir_Kind_Foreign_Module is now a library unit | Tristan Gingold | 2021-11-09 | 1 | -29/+30 |
| * | vhdl: parse PSL inherit spec. For #1899 | Tristan Gingold | 2021-11-04 | 1 | -6/+16 |
| * | vhdl: also warns on unused enumeration literal | Tristan Gingold | 2021-11-01 | 1 | -0/+2 |
| * | Add parsing of case? statement and simple test. | Brian Padalino | 2021-09-24 | 1 | -0/+7 |
| * | trans-chap9.adb: handle async_abort, sync_abort. Fix #1654 | Tristan Gingold | 2021-08-30 | 1 | -0/+16 |
| * | vhdl and psl: parse sync_abort and async_abort. For #1654 | Tristan Gingold | 2021-08-30 | 1 | -0/+7 |
| * | vhdl: remove iir_kind_anonymous_signal_declaration (now unused) | Tristan Gingold | 2021-08-24 | 1 | -26/+0 |
| * | vhdl: introduce iir_kind_association_element_by_name | Tristan Gingold | 2021-08-06 | 1 | -0/+11 |
| * | vhdl-sem_expr.adb: build element subtype for aggregate when possible. | Tristan Gingold | 2021-08-03 | 1 | -2/+2 |
| * | adjust previous commit (no identifier in Psl_Default_Clock) | Tristan Gingold | 2021-07-01 | 1 | -2/+1 |
| * | vhdl-nodes: remove Identifier from Psl_Default_Clock | Tristan Gingold | 2021-06-30 | 1 | -3/+0 |
| * | vhdl: handle mod/rem for physical. Fix #1810 | Tristan Gingold | 2021-06-30 | 1 | -0/+2 |
| * | vhdl-nodes: do not reset free hooks on initialization | Tristan Gingold | 2021-06-26 | 1 | -0/+2 |
| * | vhdl-nodes.ads: use pnodes layout for Number_Base_Type | Tristan Gingold | 2021-06-18 | 1 | -1/+8 |
| * | vhdl: remove unused Get/Set_Alias_Declaration | Tristan Gingold | 2021-05-16 | 1 | -14/+0 |
| * | vhdl: add Iir_Kind_Foreign_Module | Tristan Gingold | 2021-04-05 | 1 | -0/+31 |
| * | synth: handle pow and arctan from ieee.math_real. Fix #1665 | Tristan Gingold | 2021-02-27 | 1 | -0/+2 |
