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authorTristan Gingold <tgingold@free.fr>2022-05-29 19:55:36 +0200
committerTristan Gingold <tgingold@free.fr>2022-05-29 19:55:36 +0200
commit6607215b4ba19e42c2599cfa5c0313768013b845 (patch)
tree454d6e7cd2e4c7fa0ebc6f8d4c5d51cbdadbe24c /src/vhdl/vhdl-nodes.ads
parent232c0f8c2bdedc3d54988f80502007315757f16c (diff)
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synth-vhdl_eval: handle more operations
Diffstat (limited to 'src/vhdl/vhdl-nodes.ads')
-rw-r--r--src/vhdl/vhdl-nodes.ads13
1 files changed, 8 insertions, 5 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 8e939ad45..83c352479 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -5547,11 +5547,6 @@ package Vhdl.Nodes is
Iir_Predefined_Bit_Array_Match_Equality,
Iir_Predefined_Bit_Array_Match_Inequality,
- -- LRM08 5.3.2.4 Predefined operations on array types
- Iir_Predefined_Array_Char_To_String,
- Iir_Predefined_Bit_Vector_To_Ostring,
- Iir_Predefined_Bit_Vector_To_Hstring,
-
-- LRM08 9.2.3 Relational Operators
-- IEEE.Std_Logic_1164.Std_Ulogic
Iir_Predefined_Std_Ulogic_Match_Equality,
@@ -5565,6 +5560,11 @@ package Vhdl.Nodes is
Iir_Predefined_Std_Ulogic_Array_Match_Equality,
Iir_Predefined_Std_Ulogic_Array_Match_Inequality,
+ -- LRM08 5.3.2.4 Predefined operations on array types
+ Iir_Predefined_Array_Char_To_String,
+ Iir_Predefined_Bit_Vector_To_Ostring,
+ Iir_Predefined_Bit_Vector_To_Hstring,
+
-- -- Predefined attribute functions.
-- Iir_Predefined_Attribute_Image,
-- Iir_Predefined_Attribute_Value,
@@ -6234,6 +6234,9 @@ package Vhdl.Nodes is
subtype Iir_Predefined_Pure_Functions is Iir_Predefined_Functions range
Iir_Predefined_Boolean_And ..
Iir_Predefined_Functions'Pred (Iir_Predefined_Deallocate);
+ subtype Iir_Predefined_Operators is Iir_Predefined_Functions range
+ Iir_Predefined_Boolean_And ..
+ Iir_Predefined_Std_Ulogic_Array_Match_Inequality;
subtype Iir_Predefined_Impure_Functions is Iir_Predefined_Functions range
Iir_Predefined_Deallocate ..
Iir_Predefined_Functions'Pred (Iir_Predefined_None);