aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl/vhdl-nodes.ads
Commit message (Expand)AuthorAgeFilesLines
* vhdl-sem_inst: handle suspend_stateTristan Gingold2023-01-041-0/+17
* simul: handle force/release signal assignmentsTristan Gingold2023-01-031-2/+2
* vhdl-parse: handle 'end for' in configuration specification.Tristan Gingold2022-12-211-0/+3
* vhdl: add Get/Set_Associated_package. For #2264Tristan Gingold2022-12-181-2/+11
* vhdl-nodes: add Get/Set_Instantiated_Header.Tristan Gingold2022-12-161-0/+8
* vhdl-nodes: add Get/Set_Associated_Subprogram.Tristan Gingold2022-11-301-0/+6
* vhdl-sem_assocs: handle association with external signal names.Tristan Gingold2022-10-181-0/+3
* simul: add support for protected objectsTristan Gingold2022-09-081-1/+1
* vhdl: add iir_kind_psl_boolean_parameter node. For #2178Tristan Gingold2022-08-151-3/+23
* vhdl: add support for file subtype. Fix #2174Tristan Gingold2022-08-111-0/+21
* vhdl: add Determined_Aggregate_Flag field. For #2166Tristan Gingold2022-08-101-0/+7
* vhdl: add an owner to interface type definitionTristan Gingold2022-08-071-0/+7
* vhdl: add support for default in interface subprogram. Fix #2163Tristan Gingold2022-08-071-0/+14
* vhdl-nodes: add Get/Set_Stop_Flag. For #2150Tristan Gingold2022-07-291-0/+8
* vhdl-nodes: add Get/Set_Reference_Terminal_FlagTristan Gingold2022-07-251-0/+10
* vhdl-nodes: renaming.Tristan Gingold2022-07-211-13/+13
* vhdl: add Iir_Kinds_AMS_Signal_AttributeTristan Gingold2022-07-161-2/+10
* vhdl: avoid crash on incorrect use of signaturesTristan Gingold2022-07-021-0/+4
* vhdl: add a parent field to protected_type_declaration. Fix #2091Tristan Gingold2022-06-121-0/+3
* vhdl-nodes: add Inertial_Flag for association_element_by_expressionTristan Gingold2022-06-121-0/+9
* vhdl: recognize ieee.math_real.sign, fix is_x recogn.Tristan Gingold2022-06-111-2/+2
* vhdl-ieee-math_real: recognize more operationsTristan Gingold2022-06-061-1/+19
* synth-vhdl_eval: recognize and handle to_stdulogicvectorTristan Gingold2022-06-061-0/+7
* vhdl: recognize more predefined ieee functions and operatorsTristan Gingold2022-06-051-1/+40
* vhdl-ieee-numeric: recognize vector/scalar operationsTristan Gingold2022-06-051-3/+27
* vhdl-ieee-numeric: recognize is_x, to_x01, to_ux01 and to_x01zTristan Gingold2022-06-051-0/+12
* vhdl-ieee-std_logic_1164: recognize to_hstring, to_ostringTristan Gingold2022-06-011-0/+3
* vhdl: recognize numeric_bit.to_unsignedTristan Gingold2022-05-311-0/+10
* vhdl-nodes: move maximum/minimum out of predefined operator rangeTristan Gingold2022-05-301-27/+27
* synth-vhdl_eval: handle more operationsTristan Gingold2022-05-291-5/+8
* vhdl: recognize subprograms from std.envTristan Gingold2022-05-291-0/+7
* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-1/+40
* vhdl-nodes: remove unused fields for procedure declarationsTristan Gingold2022-05-171-0/+2
* vhdl: add suspend state pseudo decl and stmt. WIP.Tristan Gingold2022-05-171-0/+19
* vhdl-nodes: reorder, add iir_kinds_structural_statementTristan Gingold2022-04-291-9/+17
* synth: add support for subtype declaration in vunits. Fix #2033Tristan Gingold2022-04-131-0/+2
* synth: do not add info for element subtype (except for arrays).Tristan Gingold2022-04-051-0/+1
* vhdl: parse return identifier (v19)Tristan Gingold2022-03-041-0/+7
* vhdl: recognize ror/rol from ieee.numeric_std. For #1909Tristan Gingold2021-11-111-0/+4
* vhdl: Iir_Kind_Foreign_Module is now a library unitTristan Gingold2021-11-091-29/+30
* vhdl: parse PSL inherit spec. For #1899Tristan Gingold2021-11-041-6/+16
* vhdl: also warns on unused enumeration literalTristan Gingold2021-11-011-0/+2
* Add parsing of case? statement and simple test.Brian Padalino2021-09-241-0/+7
* trans-chap9.adb: handle async_abort, sync_abort. Fix #1654Tristan Gingold2021-08-301-0/+16
* vhdl and psl: parse sync_abort and async_abort. For #1654Tristan Gingold2021-08-301-0/+7
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-26/+0
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-0/+11
* vhdl-sem_expr.adb: build element subtype for aggregate when possible.Tristan Gingold2021-08-031-2/+2
* adjust previous commit (no identifier in Psl_Default_Clock)Tristan Gingold2021-07-011-2/+1
* vhdl-nodes: remove Identifier from Psl_Default_ClockTristan Gingold2021-06-301-3/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 16:47:09 +0000