| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vhdl: recognize ieee.std_logic_1164.is_x. | Tristan Gingold | 2019-12-24 | 1 | -0/+6 |
| * | vhdl-ieee-std_logic_1164: minor simplification. | Tristan Gingold | 2019-11-06 | 1 | -21/+8 |
| * | synth: handle edge operators in synth_predefined_function_call. | Tristan Gingold | 2019-11-06 | 1 | -3/+4 |
| * | vhdl: recognize rising_edge/falling_edge. | Tristan Gingold | 2019-11-06 | 1 | -6/+12 |
| * | vhdl: recognize to_bitvector. | Tristan Gingold | 2019-10-07 | 1 | -81/+72 |
| * | vhdl: recognize 1164 condition operator, handle in synth. | Tristan Gingold | 2019-08-30 | 1 | -5/+15 |
| * | initial support for reduce and/or (#900) | Pepijn de Vos | 2019-08-20 | 1 | -5/+18 |
| * | vhdl: extract vhdl.errors from errorout. | Tristan Gingold | 2019-05-08 | 1 | -1/+1 |
| * | vhdl: move ieee packages to vhdl children. | Tristan Gingold | 2019-05-05 | 1 | -0/+319 |
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index : iCE40/ghdl | |
| clone of https://github.com/ghdl/ghdl |
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