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* vhdl: handle P32 in connect_scalar. Fix #918Tristan Gingold2019-09-051-1/+2
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* ignore restrict in simulation (#897)Pepijn de Vos2019-08-202-18/+17
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* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-101-0/+1
| | | | For #877
* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-082-6/+26
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* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-075-12/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
* ghdlsynth: check top entity can be a top entity.Tristan Gingold2019-07-141-1/+1
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* vhdl: refactoring: remove configure function with string access.Tristan Gingold2019-07-141-11/+13
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* vhdl/translate: reindent.Tristan Gingold2019-07-041-1/+1
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* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-042-12/+12
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* vhdl: translate anonymous_signal_declaration.Tristan Gingold2019-07-031-8/+2
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* vhdl: add anonymous_signal_declaration.Tristan Gingold2019-07-035-11/+28
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* Error_Msg_Option: do not raise exception.Tristan Gingold2019-06-251-6/+6
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* vhdl: renames disp_vhdl to printsTristan Gingold2019-05-301-2/+2
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* trans-chap8: reverse_range returns false for is_for_loop_iterator_stable.Tristan Gingold2019-05-281-20/+23
| | | | Fix #828
* trans-chap3: improve style.Tristan Gingold2019-05-231-3/+2
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* Add simple_IO - to be used instead of Text_IO.Tristan Gingold2019-05-194-18/+11
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* trans-chap8: handle unbounded records in trans_actual. Fix #788Tristan Gingold2019-05-151-1/+1
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* vhdl: decouple errorouts a bit more.Tristan Gingold2019-05-101-4/+4
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* psl: add psl-types, psl-nodes_priv.Tristan Gingold2019-05-101-0/+1
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* vhdl: replace Iir_Int64 by Int64, and Iir_Fp64 by Fp64.Tristan Gingold2019-05-107-31/+31
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* Extract psl-errors from errorout.Tristan Gingold2019-05-101-1/+1
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* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-0817-11/+19
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* vhdl: renames iirs_walk to vhdl-nodes_walkTristan Gingold2019-05-081-1/+1
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* vhdl: renames iir_chains to vhdl.nodes_utils. Remove iir_chain_handling.Tristan Gingold2019-05-062-3/+3
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* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-0615-15/+15
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* vhdl: move nodes_meta package to vhdl child.Tristan Gingold2019-05-062-4/+4
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* vhdl: rename iirs to vhdl.nodesTristan Gingold2019-05-055-5/+5
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* vhdl: move nodes to vhdl.nodes_priv.Tristan Gingold2019-05-051-3/+3
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* vhdl: move back_end to vhdl child.Tristan Gingold2019-05-051-4/+4
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* vhdl: move evaluation to vhdl child.Tristan Gingold2019-05-055-5/+5
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* vhdl: move ieee packages to vhdl children.Tristan Gingold2019-05-052-5/+5
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* vhdl: move std_standard package to vhdl child.Tristan Gingold2019-05-058-8/+8
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* vhdl: move configuration package as a vhdl child.Tristan Gingold2019-05-053-10/+10
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* vhdl: move sem* packages to vhdl children.Tristan Gingold2019-05-054-11/+11
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* vhdl: move canon to a vhdl child package.Tristan Gingold2019-05-055-13/+15
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* vhdl: move disp_tree and disp_vhdl as vhdl child.Tristan Gingold2019-05-041-2/+2
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* vhdl: do not crash on 64 bit null range.Tristan Gingold2019-05-031-1/+3
| | | | Fix #810
* vhdl/translate: check_composite_match: rename and handle records.Tristan Gingold2019-05-036-70/+207
| | | | Fix #807
* vhdl: supports VHPIDIRECT in mcode backend.Tristan Gingold2019-04-277-89/+144
| | | | | src: add hash.ad[sb], interning.ad[sb] Automatically link with vhpidirect libraries.
* translation: adjust scan of vhpidirect string.Tristan Gingold2019-04-271-6/+5
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* trans-chap12: minor rewrite.Tristan Gingold2019-04-271-1/+3
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* grt: extract grt-dynload from grt-cvpiTristan Gingold2019-04-241-1/+1
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* vhdl: fix crash on access subtype. Fix #797Tristan Gingold2019-04-151-1/+2
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* trans-chap8: adjust condition.Tristan Gingold2019-03-251-1/+3
| | | | Fix #787
* Remove a redundant conversion.Tristan Gingold2019-02-281-1/+1
| | | | Fix #771
* vhdl: fix uvvm failure in scoreboard testbench.Tristan Gingold2019-02-072-2/+2
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* translation of aggregate: use the target type. For #737Tristan Gingold2019-01-171-1/+1
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* translation: minor refactoring.Tristan Gingold2019-01-171-12/+13
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* trans-chap3: save base type for constrained arrays.Tristan Gingold2019-01-121-0/+2
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* trans-chap7: add implicit conversion for unbounded arrays.Tristan Gingold2019-01-111-1/+8
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