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authorPepijn de Vos <pepijndevos@gmail.com>2019-08-20 21:18:41 +0200
committertgingold <tgingold@users.noreply.github.com>2019-08-20 21:18:41 +0200
commitf977ba0dd5b152e97619ecfe1d848d83f2e062ff (patch)
tree3cf86dbea48a6136946dd57a44d68de073834a5c /src/vhdl/translate
parent47a5c5eb9cc21a0f719bcc496731ec0e811e5240 (diff)
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ignore restrict in simulation (#897)
Diffstat (limited to 'src/vhdl/translate')
-rw-r--r--src/vhdl/translate/trans-chap9.adb29
-rw-r--r--src/vhdl/translate/trans-rtis.adb6
2 files changed, 17 insertions, 18 deletions
diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb
index c3d3a1af0..5211451e3 100644
--- a/src/vhdl/translate/trans-chap9.adb
+++ b/src/vhdl/translate/trans-chap9.adb
@@ -989,9 +989,9 @@ package body Trans.Chap9 is
when Iir_Kind_Process_Statement
| Iir_Kind_Sensitized_Process_Statement =>
Translate_Process_Declarations (El);
- when Iir_Kind_Psl_Default_Clock =>
- null;
- when Iir_Kind_Psl_Declaration =>
+ when Iir_Kind_Psl_Default_Clock
+ | Iir_Kind_Psl_Restrict_Directive
+ | Iir_Kind_Psl_Declaration =>
null;
when Iir_Kind_Psl_Assert_Directive
| Iir_Kind_Psl_Assume_Directive
@@ -1138,9 +1138,9 @@ package body Trans.Chap9 is
if Flag_Direct_Drivers then
Chap9.Reset_Direct_Drivers (Stmt);
end if;
- when Iir_Kind_Psl_Default_Clock =>
- null;
- when Iir_Kind_Psl_Declaration =>
+ when Iir_Kind_Psl_Default_Clock
+ | Iir_Kind_Psl_Restrict_Directive
+ | Iir_Kind_Psl_Declaration =>
null;
when Iir_Kind_Psl_Assert_Directive
| Iir_Kind_Psl_Assume_Directive
@@ -2737,12 +2737,11 @@ package body Trans.Chap9 is
when Iir_Kind_Process_Statement
| Iir_Kind_Sensitized_Process_Statement =>
null;
- when Iir_Kind_Psl_Default_Clock =>
- null;
- when Iir_Kind_Psl_Declaration
- | Iir_Kind_Psl_Endpoint_Declaration =>
- null;
- when Iir_Kind_Psl_Assert_Directive
+ when Iir_Kind_Psl_Default_Clock
+ | Iir_Kind_Psl_Declaration
+ | Iir_Kind_Psl_Endpoint_Declaration
+ | Iir_Kind_Psl_Restrict_Directive
+ | Iir_Kind_Psl_Assert_Directive
| Iir_Kind_Psl_Assume_Directive
| Iir_Kind_Psl_Cover_Directive =>
null;
@@ -2801,9 +2800,9 @@ package body Trans.Chap9 is
when Iir_Kind_Process_Statement
| Iir_Kind_Sensitized_Process_Statement =>
Elab_Process (Stmt, Base_Info);
- when Iir_Kind_Psl_Default_Clock =>
- null;
- when Iir_Kind_Psl_Declaration =>
+ when Iir_Kind_Psl_Default_Clock
+ | Iir_Kind_Psl_Restrict_Directive
+ | Iir_Kind_Psl_Declaration =>
null;
when Iir_Kind_Psl_Assert_Directive
| Iir_Kind_Psl_Assume_Directive
diff --git a/src/vhdl/translate/trans-rtis.adb b/src/vhdl/translate/trans-rtis.adb
index e618aeb9b..a36bcc076 100644
--- a/src/vhdl/translate/trans-rtis.adb
+++ b/src/vhdl/translate/trans-rtis.adb
@@ -2423,9 +2423,9 @@ package body Trans.Rtis is
Push_Identifier_Prefix (Mark, Get_Identifier (Stmt));
Generate_Instance (Stmt, Parent_Rti);
Pop_Identifier_Prefix (Mark);
- when Iir_Kind_Psl_Default_Clock =>
- null;
- when Iir_Kind_Psl_Declaration =>
+ when Iir_Kind_Psl_Default_Clock
+ | Iir_Kind_Psl_Restrict_Directive
+ | Iir_Kind_Psl_Declaration =>
null;
when Iir_Kind_Psl_Assert_Directive
| Iir_Kind_Psl_Assume_Directive