vhdl: move sem* packages to vhdl children.

4 files changed, 11 insertions, 11 deletions

diff --git a/src/vhdl/translate/ortho_front.adb b/src/vhdl/translate/ortho_front.adb
index 208348ef4..3fc6f4e81 100644
--- a/src/vhdl/translate/ortho_front.adb
+++ b/src/vhdl/translate/ortho_front.adb
@@ -29,8 +29,8 @@ with Std_Package;
 with Flags;
 with Configuration;
 with Translation;
-with Sem;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
 with Errorout; use Errorout;
 with Errorout.Console;
 with GNAT.OS_Lib;
@@ -317,7 +317,7 @@ package body Ortho_Front is
       --  Do late analysis checks.
       Design := Get_First_Design_Unit (New_Design_File);
       while Is_Valid (Design) loop
-         Sem.Sem_Analysis_Checks_List
+         Vhdl.Sem.Sem_Analysis_Checks_List
            (Design, Is_Warning_Enabled (Warnid_Delayed_Checks));
          Design := Get_Chain (Design);
       end loop;
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index 1e39d3456..1659d54fb 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -22,8 +22,8 @@ with Std_Package; use Std_Package;
 with Iirs_Utils; use Iirs_Utils;
 with Libraries;
 with Flags;
-with Sem;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
 with Trans.Chap1;
 with Trans.Chap2;
 with Trans.Chap6;
@@ -550,7 +550,7 @@ package body Trans.Chap12 is
       if Flag_Load_All_Design_Units then
          for I in Design_Units.First .. Design_Units.Last loop
             Unit := Design_Units.Table (I);
-            Sem.Sem_Analysis_Checks_List (Unit, False);
+            Vhdl.Sem.Sem_Analysis_Checks_List (Unit, False);
             --  There cannot be remaining checks to do.
             pragma Assert
               (Get_Analysis_Checks_List (Unit) = Null_Iir_List);
diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb
index 01703b842..433d18443 100644
--- a/src/vhdl/translate/trans-chap2.adb
+++ b/src/vhdl/translate/trans-chap2.adb
@@ -19,7 +19,7 @@
 with Std_Names;
 with Std_Package; use Std_Package;
 with Errorout; use Errorout;
-with Sem_Inst;
+with Vhdl.Sem_Inst;
 with Nodes_Meta;
 with Iirs_Utils; use Iirs_Utils;
 with Trans.Chap3;
@@ -1377,7 +1377,7 @@ package body Trans.Chap2 is
          Kind      : constant Iir_Kind := Get_Kind (N);
          Fields    : constant Fields_Array := Get_Fields (Kind);
          F         : Fields_Enum;
-         Orig      : constant Iir := Sem_Inst.Get_Origin (N);
+         Orig      : constant Iir := Vhdl.Sem_Inst.Get_Origin (N);
          pragma Assert (Orig /= Null_Iir);
          Orig_Info : constant Ortho_Info_Acc := Get_Info (Orig);
          Info      : Ortho_Info_Acc;
@@ -1489,7 +1489,7 @@ package body Trans.Chap2 is
    begin
       Inter := Chain;
       while Inter /= Null_Iir loop
-         Orig := Sem_Inst.Get_Origin (Inter);
+         Orig := Vhdl.Sem_Inst.Get_Origin (Inter);
          Orig_Info := Get_Info (Orig);
 
          Info := Add_Info (Inter, Orig_Info.Kind);
diff --git a/src/vhdl/translate/translation.adb b/src/vhdl/translate/translation.adb
index 4f66723cf..4c5ba5eca 100644
--- a/src/vhdl/translate/translation.adb
+++ b/src/vhdl/translate/translation.adb
@@ -26,7 +26,7 @@ with Str_Table;
 with Files_Map;
 with Iirs_Utils; use Iirs_Utils;
 with Std_Package; use Std_Package;
-with Sem_Specs;
+with Vhdl.Sem_Specs;
 with Libraries;
 with Std_Names;
 with Vhdl.Canon;
@@ -109,7 +109,7 @@ package body Translation is
    is
       --  Look for 'FOREIGN.
       Attr : constant Iir_Attribute_Value :=
-        Sem_Specs.Find_Attribute_Value (Decl, Std_Names.Name_Foreign);
+        Vhdl.Sem_Specs.Find_Attribute_Value (Decl, Std_Names.Name_Foreign);
       pragma Assert (Attr /= Null_Iir);
       Spec : constant Iir_Attribute_Specification :=
         Get_Attribute_Specification (Attr);