iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	sem_inst: fix relocation of instances in instances.	Tristan Gingold	2017-12-21	1	-0/+1
*	Rework list implementation, use iterator.	Tristan Gingold	2017-11-11	1	-4/+11
*	Remove List_Others, cleanup lists.	Tristan Gingold	2017-11-08	1	-2/+1
*	Use Flist for array indexes.	Tristan Gingold	2017-11-06	1	-0/+31
*	Add extended locations (elocations). Still WIP	Tristan Gingold	2017-10-18	1	-1/+0
*	Rename In_Conversion/Out_Conversion to Actual_Conversion/Formal_Conversion.	Tristan Gingold	2017-09-13	1	-1/+1
*	Silent spurious warning.	Tristan Gingold	2017-06-14	1	-0/+5
*	Translation: separate subprogram translation spec and body.	Tristan Gingold	2017-05-18	1	-2/+4
*	Create default value for ports.	Tristan Gingold	2017-05-09	1	-201/+276
*	vhdl08: more on unbounded records (WIP)	Tristan Gingold	2017-02-23	1	-1/+1
*	removing PSL coverage hit default report	Thomas Hiscock	2017-01-05	1	-2/+4
*	translate: rename get_array_base to get_composite_base	Tristan Gingold	2017-01-02	1	-2/+2
*	translate: refactoring for ortho_info_type.	Tristan Gingold	2016-12-30	1	-12/+12
*	ownership: check tree after sem and canon.	Tristan Gingold	2016-11-05	1	-4/+14
*	canon: do not set formal of association by position.	Tristan Gingold	2016-10-19	1	-14/+21
*	iirs: rename base_type to number_base_type to avoid confusion.	Tristan Gingold	2016-10-13	1	-1/+1
*	Rework AST to setup ownership and reference policy.	Tristan Gingold	2016-10-11	1	-1/+2
*	iirs: add Forward_Ref links	Tristan Gingold	2016-09-30	1	-1/+2
*	vhdl08: add support of case-generate statement	Tristan Gingold	2016-07-07	1	-91/+326
*	Initial support of direct recursive instantiation.	Tristan Gingold	2016-07-03	1	-5/+17
*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	1	-35/+69
*	PSL: add counters, generate rti and add --psl-report	Tristan Gingold	2016-03-18	1	-25/+12
*	PSL translate: handle bit type.	Tristan Gingold	2016-03-18	1	-4/+8
*	translate: separate decl and stmt elab subprograms.	Tristan Gingold	2016-02-23	1	-22/+195
*	translate: minor reformating.	Tristan Gingold	2016-02-21	1	-24/+19
*	Tentative fix for issue43.	Tristan Gingold	2016-02-17	1	-1/+1
*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-14	1	-1/+7
*	PSL: move canon code to canon.adb	Tristan Gingold	2016-02-14	1	-50/+26
*	Pass signal values to interfaces. 'sigptr' optimization.	Tristan Gingold	2015-12-18	1	-2/+6
*	Suppress stack switching; save process state in secondary stack.	Tristan Gingold	2015-09-04	1	-0/+29
*	Translate: explicitly clean transient types.	Tristan Gingold	2015-09-02	1	-1/+5
*	Allow allocators in default value of subprograms	Tristan Gingold	2015-08-29	1	-48/+116
*	Replace fat accesses by bounds accesses	Tristan Gingold	2015-08-29	1	-37/+32
*	Rework procedure calls, now use a record to pass parameters.	Tristan Gingold	2015-06-05	1	-2/+1
*	Fix entity instantiation with extended identifier.	Tristan Gingold	2015-03-31	1	-3/+5
*	Keep and handle simple name for Block_Specification.	Tristan Gingold	2015-01-16	1	-2/+2
*	Fix ticket #29: add instance label in created symbols name.	Tristan Gingold	2015-01-11	1	-1/+3
*	Handle vhdl08 if generate statements	Tristan Gingold	2015-01-07	1	-177/+249
*	Rework for vhdl08 generate: change rtis.	Tristan Gingold	2015-01-04	1	-1/+2
*	Initial rework for vhdl 2008 generate statements.	Tristan Gingold	2015-01-03	1	-71/+97
*	trans-chap9: fix invalid generation of ortho code.	Tristan Gingold	2014-11-20	1	-4/+5
*	Split translation into child packages.	Tristan Gingold	2014-11-09	1	-0/+1953