| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | update license headers | umarcor | 2021-01-14 | 1 | -11/+9 |
| | | |||||
| * | src/vhd: remove use of chapter sign in comment to have on ASCII characters | Tristan Gingold | 2021-01-09 | 1 | -2/+2 |
| | | | | | (except for vhdl-scanner) | ||||
| * | grt: slightly simplify the interface. | Tristan Gingold | 2020-04-02 | 1 | -3/+3 |
| | | |||||
| * | psl: keep denoting names in the PSL ast. | Tristan Gingold | 2020-03-13 | 1 | -1/+2 |
| | | |||||
| * | vhdl: remove severity from cover, report and severity from assume. | Tristan Gingold | 2019-08-08 | 1 | -1/+1 |
| | | |||||
| * | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 1 | -2/+9 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code | ||||
| * | vhdl: rename Cover_Statement to Cover_Directive. | Tristan Gingold | 2019-07-04 | 1 | -3/+3 |
| | | |||||
| * | vhdl: move annotations from simul to vhdl. | Tristan Gingold | 2019-06-29 | 1 | -1/+1 |
| | | |||||
| * | Add simple_IO - to be used instead of Text_IO. | Tristan Gingold | 2019-05-19 | 1 | -3/+3 |
| | | |||||
| * | psl: add psl-types, psl-nodes_priv. | Tristan Gingold | 2019-05-10 | 1 | -0/+1 |
| | | |||||
| * | Extract psl-errors from errorout. | Tristan Gingold | 2019-05-10 | 1 | -1/+1 |
| | | |||||
| * | vhdl: extract vhdl.errors from errorout. | Tristan Gingold | 2019-05-08 | 1 | -0/+1 |
| | | |||||
| * | vhdl: move iirs_utils to vhdl.utils | Tristan Gingold | 2019-05-06 | 1 | -1/+1 |
| | | |||||
| * | vhdl: move ieee packages to vhdl children. | Tristan Gingold | 2019-05-05 | 1 | -2/+2 |
| | | |||||
| * | vhdl: move std_standard package to vhdl child. | Tristan Gingold | 2019-05-05 | 1 | -2/+2 |
| | | |||||
| * | fix gnat8 errors for libghdlsynth targets | Stefan Biereigel | 2019-03-13 | 1 | -2/+0 |
| | | |||||
| * | simul: handle PSL assert finalizer. | Tristan Gingold | 2019-01-06 | 1 | -4/+57 |
| | | |||||
| * | simul: handle psl endpoints (and adjust issue45). | Tristan Gingold | 2017-12-21 | 1 | -11/+24 |
| | | |||||
| * | simul: fix issue228. | Tristan Gingold | 2017-12-21 | 1 | -3/+5 |
| | | |||||
| * | simul: create initial driver value. | Tristan Gingold | 2017-12-21 | 1 | -18/+26 |
| | | |||||
| * | simul-debugger: add run command. | Tristan Gingold | 2017-12-20 | 1 | -5/+18 |
| | | |||||
| * | grt: reorganize simulation loop. | Tristan Gingold | 2017-12-20 | 1 | -2/+21 |
| | | |||||
| * | simul: support type conversion in association. | Tristan Gingold | 2017-12-11 | 1 | -1/+1 |
| | | |||||
| * | simul: handle package interface, remove iir_value_environment. | Tristan Gingold | 2017-12-05 | 1 | -4/+2 |
| | | |||||
| * | simul: add iir_value_instance, remove package_instances. | Tristan Gingold | 2017-12-03 | 1 | -0/+2 |
| | | |||||
| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -0/+1145 |
 |
index : iCE40/ghdl | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |