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author | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:00:35 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:05:12 +0200 |
commit | 3fa8d9eb8b700044d149bdf12da6cb023568b8c0 (patch) | |
tree | 3cbd54423bad53e6db401e43ef0e4216833cd8b9 /src/vhdl/simulate/simul-simulation-main.adb | |
parent | 85d360929d13e6b0bcb082f144883a43f402ce22 (diff) | |
download | ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.tar.gz ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.tar.bz2 ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.zip |
vhdl: move ieee packages to vhdl children.
Diffstat (limited to 'src/vhdl/simulate/simul-simulation-main.adb')
-rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index 2d0558308..141e1fd2d 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -29,7 +29,7 @@ with Trans_Analyzes; with Simul.Elaboration; use Simul.Elaboration; with Simul.Execution; use Simul.Execution; with Simul.Annotations; use Simul.Annotations; -with Ieee.Std_Logic_1164; +with Vhdl.Ieee.Std_Logic_1164; with Grt.Main; with Simul.Debugger; use Simul.Debugger; with Simul.Debugger.AMS; @@ -381,7 +381,7 @@ package body Simul.Simulation.Main is Res := Execute_Expression (Instance, E); if Rtype = Vhdl.Std_Package.Boolean_Type_Definition then return Res.B1 = True; - elsif Rtype = Ieee.Std_Logic_1164.Std_Ulogic_Type then + elsif Rtype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type then return Res.E8 = 3 or Res.E8 = 7; -- 1 or H else Error_Kind ("execute_psl_expr", Expr); |