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| author | Tristan Gingold <tgingold@free.fr> | 2019-05-05 07:49:25 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:05:11 +0200 |
| commit | 85d360929d13e6b0bcb082f144883a43f402ce22 (patch) | |
| tree | f8d8135e12393588b7704318f26304dfab272658 /src/vhdl/simulate/simul-simulation-main.adb | |
| parent | 3c48cc2a70085eef63718e622b3d1a7b75a2f36f (diff) | |
| download | ghdl-85d360929d13e6b0bcb082f144883a43f402ce22.tar.gz ghdl-85d360929d13e6b0bcb082f144883a43f402ce22.tar.bz2 ghdl-85d360929d13e6b0bcb082f144883a43f402ce22.zip | |
vhdl: move std_standard package to vhdl child.
Diffstat (limited to 'src/vhdl/simulate/simul-simulation-main.adb')
| -rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index 7d6f0e7c7..2d0558308 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -24,7 +24,7 @@ with Errorout; use Errorout; with PSL.Nodes; with PSL.NFAs; with PSL.NFAs.Utils; -with Std_Package; +with Vhdl.Std_Package; with Trans_Analyzes; with Simul.Elaboration; use Simul.Elaboration; with Simul.Execution; use Simul.Execution; @@ -379,7 +379,7 @@ package body Simul.Simulation.Main is Res : Iir_Value_Literal_Acc; begin Res := Execute_Expression (Instance, E); - if Rtype = Std_Package.Boolean_Type_Definition then + if Rtype = Vhdl.Std_Package.Boolean_Type_Definition then return Res.B1 = True; elsif Rtype = Ieee.Std_Logic_1164.Std_Ulogic_Type then return Res.E8 = 3 or Res.E8 = 7; -- 1 or H |