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* synth-vhdl_eval: complete vector reduce operationsTristan Gingold2022-05-311-7/+21
* synth-vhdl_eval: handle shift and rotationsTristan Gingold2022-05-311-6/+29
* synth-vhdl_eval: handle vector match, numeric_bit.to_unsignedTristan Gingold2022-05-312-7/+73
* synth-vhdl_stmts: do not convert out variable on callTristan Gingold2022-05-311-3/+8
* synth-vhdl_stmts: export Synth_Subprogram_Back_AssociationTristan Gingold2022-05-312-7/+15
* synth-vhdl_static_proc: handle write_realTristan Gingold2022-05-311-0/+32
* synth-vhdl_eval: handle more operations (to_string, match)Tristan Gingold2022-05-312-23/+229
* synth-vhdl_eval: handle more operatorsTristan Gingold2022-05-303-26/+402
* synth-vhdl_static_proc: add hook for std.env.finishTristan Gingold2022-05-302-0/+12
* synth-vhdl_oper: add hooks for bit edgeTristan Gingold2022-05-302-0/+15
* vhdl-nodes: move maximum/minimum out of predefined operator rangeTristan Gingold2022-05-302-37/+40
* elab-vhdl_objtypes: bit and logic types also have a rangeTristan Gingold2022-05-302-6/+13
* synth-vhdl_eval: handle more operationsTristan Gingold2022-05-293-17/+210
* synth-vhdl_eval: handle resolution_limitTristan Gingold2022-05-291-0/+3
* elab-debugger: export more subprogramsTristan Gingold2022-05-291-0/+6
* synth-vhdl_stmts: export two procedures, adjust assertion messageTristan Gingold2022-05-292-5/+10
* synth-vhdl_oper: add hook for falling edge, handle aliases.Tristan Gingold2022-05-293-3/+13
* synth-vhdl_eval: handle more operationsTristan Gingold2022-05-291-0/+30
* elab-vhdl_objtypes: add unshare with areapoolTristan Gingold2022-05-292-0/+13
* synth: handle suspend state declaration and statementTristan Gingold2022-05-272-0/+16
* elab-debugger: add Debug_TimeTristan Gingold2022-05-272-1/+16
* elab-vhdl_debug: handle records in disp_memtyp.Tristan Gingold2022-05-272-4/+32
* elab-vhdl_objtypes: add Create_Memory_U32 (for states)Tristan Gingold2022-05-272-3/+19
* vhdl-canon: add Canon_Add_Suspend_StateTristan Gingold2022-05-261-0/+6
* synth: move procedure call copyback values in contextTristan Gingold2022-05-253-79/+82
* vhdl: move Is_Copyback_Parameter to vhdl-utilsTristan Gingold2022-05-251-12/+2
* synth: add value_dyn_alias in elab-vhdl_valuesTristan Gingold2022-05-258-72/+203
* elab-vhdl_objtypes: use value_offsets for record elements offset.Tristan Gingold2022-05-2412-56/+52
* synth-vhdl_stmts: minor refactoringTristan Gingold2022-05-241-12/+23
* synth-vhdl_eval: handle element-element concatenationTristan Gingold2022-05-241-0/+18
* elab-vhdl_values-debug: slightly improve outputTristan Gingold2022-05-241-2/+6
* synth-vhdl_stmts: rework synth_subprogram_associationTristan Gingold2022-05-231-35/+35
* synth-vhdl_oper: add an hook for rising_edgeTristan Gingold2022-05-233-4/+13
* elab-vhdl_objtypes: replace Is_Synth by WkindTristan Gingold2022-05-223-23/+40
* synth: use same elements for unbounded arrays and vectorsTristan Gingold2022-05-229-70/+36
* synth: also use one-dimensional unbounded arrays for objtypesTristan Gingold2022-05-226-58/+66
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-2214-131/+107
* elab-vhdl_values-debug: improve debug_typ outputTristan Gingold2022-05-221-14/+37
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-2217-552/+340
* synth-vhdl_stmts: write generic procedure Assign_Aggregate.Tristan Gingold2022-05-212-14/+29
* synth-vhdl_expr: avoid a memocy copyTristan Gingold2022-05-211-3/+7
* synth/elab-vhdl_values: use a proper type for signal_indexTristan Gingold2022-05-195-7/+11
* synth-vhdl_stmts: avoid a crash after an error. Fix #2063Tristan Gingold2022-05-181-1/+4
* synth-vhdl_stmts: add comments about report statementsTristan Gingold2022-05-181-5/+51
* elab-vhdl_context: remove cur_stmt from contextTristan Gingold2022-05-172-21/+0
* synth-vhdl_stmts: add a commentTristan Gingold2022-05-171-0/+2
* synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062Tristan Gingold2022-05-171-0/+1
* elab-vhdl_debug(disp_instance_path): can also display componentsTristan Gingold2022-05-162-7/+23
* elab-vhdl_debug: factorize code, make Put_Dir publicTristan Gingold2022-05-162-12/+6
* elab-vhdl_values: rename signal_index to signal_index_typeTristan Gingold2022-05-153-5/+5
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