synth: merge value for type_vector and type_array

14 files changed, 107 insertions, 131 deletions

diff --git a/src/synth/elab-vhdl_debug.adb b/src/synth/elab-vhdl_debug.adb
index 6b137b892..6c86f6e0a 100644
--- a/src/synth/elab-vhdl_debug.adb
+++ b/src/synth/elab-vhdl_debug.adb
@@ -150,7 +150,7 @@ package body Elab.Vhdl_Debug is
            | Type_Logic =>
             Disp_Discrete_Value (Read_Discrete (M), Get_Base_Type (Vtype));
          when Type_Vector =>
-            Disp_Value_Vector (M, Vtype, M.Typ.Vbound);
+            Disp_Value_Vector (M, Vtype, M.Typ.Abound);
          when Type_Array =>
             Disp_Value_Array (M, Vtype);
          when Type_Float =>
@@ -234,7 +234,7 @@ package body Elab.Vhdl_Debug is
             Put ("float");
          when Type_Vector =>
             Put ("vector (");
-            Disp_Bound_Type (Typ.Vbound);
+            Disp_Bound_Type (Typ.Abound);
             Put (')');
          when Type_Unbounded_Vector =>
             Put ("unbounded_vector");
diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb
index 6982b825f..fd57960cb 100644
--- a/src/synth/elab-vhdl_expr.adb
+++ b/src/synth/elab-vhdl_expr.adb
@@ -446,10 +446,8 @@ package body Elab.Vhdl_Expr is
      (Typ : Type_Acc; Bnd : out Bound_Type; El_Typ : out Type_Acc) is
    begin
       case Typ.Kind is
-         when Type_Vector =>
-            El_Typ := Typ.Vec_El;
-            Bnd := Typ.Vbound;
-         when Type_Array =>
+         when Type_Array
+           | Type_Vector =>
             pragma Assert (Typ.Alast);
             El_Typ := Typ.Arr_El;
             Bnd := Typ.Abound;
@@ -466,7 +464,7 @@ package body Elab.Vhdl_Expr is
       case Btyp.Kind is
          when Type_Vector =>
             pragma Assert (El_Typ.Kind in Type_Nets);
-            Res := Create_Vector_Type (Bnd, Btyp.Vec_El);
+            Res := Create_Vector_Type (Bnd, Btyp.Arr_El);
          when Type_Unbounded_Vector =>
             pragma Assert (El_Typ.Kind in Type_Nets);
             Res := Create_Vector_Type (Bnd, Btyp.Uvec_El);
@@ -1004,9 +1002,8 @@ package body Elab.Vhdl_Expr is
       Pos : Nat8;
    begin
       case Str_Typ.Kind is
-         when Type_Vector =>
-            Bounds := Str_Typ.Vbound;
-         when Type_Array =>
+         when Type_Vector
+           | Type_Array =>
             Bounds := Str_Typ.Abound;
          when Type_Unbounded_Vector
             | Type_Unbounded_Array =>
diff --git a/src/synth/elab-vhdl_objtypes.adb b/src/synth/elab-vhdl_objtypes.adb
index 3040f1874..cd44324a7 100644
--- a/src/synth/elab-vhdl_objtypes.adb
+++ b/src/synth/elab-vhdl_objtypes.adb
@@ -77,14 +77,8 @@ package body Elab.Vhdl_Objtypes is
             return L.Drange = R.Drange;
          when Type_Float =>
             return L.Frange = R.Frange;
-         when Type_Vector =>
-            return L.Vbound = R.Vbound
-              and then Are_Types_Equal (L.Vec_El, R.Vec_El);
-         when Type_Unbounded_Vector =>
-            return Are_Types_Equal (L.Uvec_El, R.Uvec_El);
-         when Type_Slice =>
-            return Are_Types_Equal (L.Slice_El, R.Slice_El);
-         when Type_Array =>
+         when Type_Array
+           | Type_Vector =>
             if L.Alast /= R.Alast then
                return False;
             end if;
@@ -95,6 +89,10 @@ package body Elab.Vhdl_Objtypes is
          when Type_Unbounded_Array =>
             return L.Uarr_Ndim = R.Uarr_Ndim
               and then Are_Types_Equal (L.Uarr_El, R.Uarr_El);
+         when Type_Unbounded_Vector =>
+            return Are_Types_Equal (L.Uvec_El, R.Uvec_El);
+         when Type_Slice =>
+            return Are_Types_Equal (L.Slice_El, R.Slice_El);
          when Type_Record
            | Type_Unbounded_Record =>
             if L.Rec.Len /= R.Rec.Len then
@@ -279,14 +277,16 @@ package body Elab.Vhdl_Objtypes is
       subtype Vector_Type_Type is Type_Type (Type_Vector);
       function Alloc is new Areapools.Alloc_On_Pool_Addr (Vector_Type_Type);
    begin
+      pragma Assert (El_Type.Kind in Type_Nets);
       return To_Type_Acc
         (Alloc (Current_Pool, (Kind => Type_Vector,
                                Is_Synth => True,
                                Al => El_Type.Al,
                                Sz => El_Type.Sz * Size_Type (Bnd.Len),
                                W => Bnd.Len,
-                               Vbound => Bnd,
-                               Vec_El => El_Type)));
+                               Alast => True,
+                               Abound => Bnd,
+                               Arr_El => El_Type)));
    end Create_Vector_Type;
 
    function Create_Slice_Type (Len : Uns32; El_Type : Type_Acc)
@@ -391,9 +391,8 @@ package body Elab.Vhdl_Objtypes is
    function Get_Array_Element (Arr_Type : Type_Acc) return Type_Acc is
    begin
       case Arr_Type.Kind is
-         when Type_Vector =>
-            return Arr_Type.Vec_El;
-         when Type_Array =>
+         when Type_Vector
+           | Type_Array =>
             return Arr_Type.Arr_El;
          when Type_Unbounded_Array =>
             return Arr_Type.Uarr_El;
@@ -408,12 +407,8 @@ package body Elab.Vhdl_Objtypes is
                             return Bound_Type is
    begin
       case Typ.Kind is
-         when Type_Vector =>
-            if Dim /= 1 then
-               raise Internal_Error;
-            end if;
-            return Typ.Vbound;
-         when Type_Array =>
+         when Type_Vector
+           | Type_Array =>
             if Dim /= 1 then
                raise Internal_Error;
             end if;
@@ -580,14 +575,14 @@ package body Elab.Vhdl_Objtypes is
 
    function Vec_Length (Typ : Type_Acc) return Iir_Index32 is
    begin
-      return Iir_Index32 (Typ.Vbound.Len);
+      return Iir_Index32 (Typ.Abound.Len);
    end Vec_Length;
 
    function Get_Array_Flat_Length (Typ : Type_Acc) return Iir_Index32 is
    begin
       case Typ.Kind is
          when Type_Vector =>
-            return Iir_Index32 (Typ.Vbound.Len);
+            return Iir_Index32 (Typ.Abound.Len);
          when Type_Array =>
             declare
                Len : Uns32;
@@ -616,12 +611,11 @@ package body Elab.Vhdl_Objtypes is
    function Get_Bound_Length (T : Type_Acc) return Uns32 is
    begin
       case T.Kind is
-         when Type_Vector =>
-            return T.Vbound.Len;
+         when Type_Vector
+           | Type_Array =>
+            return T.Abound.Len;
          when Type_Slice =>
             return T.W;
-         when Type_Array =>
-            return T.Abound.Len;
          when others =>
             raise Internal_Error;
       end case;
diff --git a/src/synth/elab-vhdl_objtypes.ads b/src/synth/elab-vhdl_objtypes.ads
index d7f246d8e..c9f1a4894 100644
--- a/src/synth/elab-vhdl_objtypes.ads
+++ b/src/synth/elab-vhdl_objtypes.ads
@@ -140,18 +140,16 @@ package Elab.Vhdl_Objtypes is
             Drange : Discrete_Range_Type;
          when Type_Float =>
             Frange : Float_Range_Type;
-         when Type_Vector =>
-            Vbound : Bound_Type;
-            Vec_El : Type_Acc;
-         when Type_Unbounded_Vector =>
-            Uvec_El : Type_Acc;
-            Uvec_Idx1 : Type_Acc;
          when Type_Slice =>
             Slice_El : Type_Acc;
-         when Type_Array =>
+         when Type_Array
+           | Type_Vector =>
             Abound : Bound_Type;
             Alast : Boolean;  --  True for the last dimension
             Arr_El : Type_Acc;
+         when Type_Unbounded_Vector =>
+            Uvec_El : Type_Acc;
+            Uvec_Idx1 : Type_Acc;
          when Type_Unbounded_Array =>
             Uarr_Ndim : Dim_Type;
             Uarr_El : Type_Acc;
diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb
index dfa14bc6c..c149c2eb0 100644
--- a/src/synth/elab-vhdl_values-debug.adb
+++ b/src/synth/elab-vhdl_values-debug.adb
@@ -68,9 +68,9 @@ package body Elab.Vhdl_Values.Debug is
             Put ("vector ");
             Debug_Typ_Phys (T);
             Put (" (");
-            Debug_Bound (T.Vbound, True);
+            Debug_Bound (T.Abound, True);
             Put (") of ");
-            Debug_Typ1 (T.Vec_El);
+            Debug_Typ1 (T.Arr_El);
          when Type_Array =>
             Put ("arr ");
             Debug_Typ_Phys (T);
@@ -151,9 +151,9 @@ package body Elab.Vhdl_Values.Debug is
          when Type_Logic =>
             Put ("logic");
          when Type_Vector =>
-            Debug_Type_Short (T.Vec_El);
+            Debug_Type_Short (T.Arr_El);
             Put ("_vec(");
-            Debug_Bound (T.Vbound, False);
+            Debug_Bound (T.Abound, False);
             Put (")");
          when Type_Array =>
             declare
@@ -202,9 +202,9 @@ package body Elab.Vhdl_Values.Debug is
             Put_Uns32 (Uns32 (Read_U8 (M.Mem)));
          when Type_Vector =>
             Put ("vector (");
-            Debug_Bound (M.Typ.Vbound, True);
+            Debug_Bound (M.Typ.Abound, True);
             Put ("): ");
-            for I in 1 .. M.Typ.Vbound.Len loop
+            for I in 1 .. M.Typ.Abound.Len loop
                Put_Uns32 (Uns32 (Read_U8 (M.Mem + Size_Type (I - 1))));
             end loop;
          when Type_Array =>
diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb
index 8d14048cb..3187671db 100644
--- a/src/synth/elab-vhdl_values.adb
+++ b/src/synth/elab-vhdl_values.adb
@@ -162,11 +162,6 @@ package body Elab.Vhdl_Values is
       return (Vtype, Create_Value_File (File));
    end Create_Value_File;
 
-   function Vec_Length (Typ : Type_Acc) return Iir_Index32 is
-   begin
-      return Iir_Index32 (Typ.Vbound.Len);
-   end Vec_Length;
-
    function Create_Value_Alias
      (Obj : Valtyp; Off : Value_Offsets; Typ : Type_Acc) return Valtyp
    is
@@ -376,12 +371,13 @@ package body Elab.Vhdl_Values is
             Write_Discrete (M, Typ, Typ.Drange.Left);
          when Type_Float =>
             Write_Fp64 (M, Typ.Frange.Left);
-         when Type_Vector =>
+         when Type_Array
+           | Type_Vector =>
             declare
-               Len : constant Iir_Index32 := Vec_Length (Typ);
-               El_Typ : constant Type_Acc := Typ.Vec_El;
+               Len : constant Uns32 := Get_Bound_Length (Typ);
+               El_Typ : constant Type_Acc := Typ.Arr_El;
             begin
-               for I in 1 .. Len loop
+               for I in 1 .. Iir_Index32 (Len) loop
                   Write_Value_Default (Arr_Index (M, I - 1, El_Typ), El_Typ);
                end loop;
             end;
@@ -391,15 +387,6 @@ package body Elab.Vhdl_Values is
             raise Internal_Error;
          when Type_Slice =>
             raise Internal_Error;
-         when Type_Array =>
-            declare
-               Len : constant Uns32 := Get_Bound_Length (Typ);
-               El_Typ : constant Type_Acc := Typ.Arr_El;
-            begin
-               for I in 1 .. Iir_Index32 (Len) loop
-                  Write_Value_Default (Arr_Index (M, I - 1, El_Typ), El_Typ);
-               end loop;
-            end;
          when Type_Record =>
             for I in Typ.Rec.E'Range loop
                Write_Value_Default (M + Typ.Rec.E (I).Moff, Typ.Rec.E (I).Typ);
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb
index dfb4a78d6..8243a89ff 100644
--- a/src/synth/synth-disp_vhdl.adb
+++ b/src/synth/synth-disp_vhdl.adb
@@ -157,7 +157,7 @@ package body Synth.Disp_Vhdl is
          when Iir_Kind_Array_Type_Definition =>
             if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type then
                --  Nothing to do.
-               W := Typ.Vbound.Len;
+               W := Typ.Abound.Len;
                Disp_In_Lhs (Mname, Off, W, Full);
                Put (Pfx);
                if W = 1 then
@@ -167,7 +167,7 @@ package body Synth.Disp_Vhdl is
                end if;
                Put_Line (";");
             elsif Is_Std_Logic_Array (Btype) then
-               W := Typ.Vbound.Len;
+               W := Typ.Abound.Len;
                Disp_In_Lhs (Mname, Off, W, Full);
                if W > 1 then
                   if Full then
@@ -189,7 +189,7 @@ package body Synth.Disp_Vhdl is
                end if;
                Put_Line (";");
             elsif Btype = Vhdl.Std_Package.Bit_Vector_Type_Definition then
-               W := Typ.Vbound.Len;
+               W := Typ.Abound.Len;
                Disp_In_Lhs (Mname, Off, W, Full);
                Put ("to_stdlogicvector (" & Pfx & ")");
                Put_Line (";");
@@ -340,7 +340,7 @@ package body Synth.Disp_Vhdl is
          when Iir_Kind_Array_Type_Definition =>
             if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type then
                --  Nothing to do.
-               W := Typ.Vbound.Len;
+               W := Typ.Abound.Len;
                Put ("  " & Pfx);
                if W = 1 then
                   Put (" (" & Pfx & "'left)");
@@ -350,7 +350,7 @@ package body Synth.Disp_Vhdl is
                Put_Line (";");
             elsif Btype = Vhdl.Std_Package.Bit_Vector_Type_Definition then
                --  Nothing to do.
-               W := Typ.Vbound.Len;
+               W := Typ.Abound.Len;
                Put ("  " & Pfx & " <= ");
                if W = 1 then
                   --  This is an array of length 1.  A scalar is used in the
@@ -366,7 +366,7 @@ package body Synth.Disp_Vhdl is
                Put_Line (");");
             elsif Is_Std_Logic_Array (Btype) then
                --  unsigned, signed or a compatible array.
-               W := Typ.Vbound.Len;
+               W := Typ.Abound.Len;
                Put ("  " & Pfx & " <= ");
                Put (Name_Table.Image (Get_Identifier
                                         (Get_Type_Declarator (Btype))));
diff --git a/src/synth/synth-ieee-numeric_std.adb b/src/synth/synth-ieee-numeric_std.adb
index f8b7bc960..7f5d0cbf2 100644
--- a/src/synth/synth-ieee-numeric_std.adb
+++ b/src/synth/synth-ieee-numeric_std.adb
@@ -48,19 +48,19 @@ package body Synth.Ieee.Numeric_Std is
 
    function Create_Res_Type (Otyp : Type_Acc; Len : Uns32) return Type_Acc is
    begin
-      if Otyp.Vbound.Len = Len
-        and then Otyp.Vbound.Right = 0
-        and then Otyp.Vbound.Dir = Dir_Downto
+      if Otyp.Abound.Len = Len
+        and then Otyp.Abound.Right = 0
+        and then Otyp.Abound.Dir = Dir_Downto
       then
-         pragma Assert (Otyp.Vbound.Left = Int32 (Len) - 1);
+         pragma Assert (Otyp.Abound.Left = Int32 (Len) - 1);
          return Otyp;
       end if;
-      return Create_Vec_Type_By_Length (Len, Otyp.Vec_El);
+      return Create_Vec_Type_By_Length (Len, Otyp.Arr_El);
    end Create_Res_Type;
 
    procedure Fill (Res : Memtyp; V : Std_Ulogic) is
    begin
-      for I in 1 .. Res.Typ.Vbound.Len loop
+      for I in 1 .. Res.Typ.Abound.Len loop
          Write_Std_Logic (Res.Mem, I - 1, V);
       end loop;
    end Fill;
@@ -344,8 +344,8 @@ package body Synth.Ieee.Numeric_Std is
    function Add_Vec_Vec (L, R : Memtyp; Signed : Boolean; Loc : Syn_Src)
                          return Memtyp
    is
-      Llen : constant Uns32 := L.Typ.Vbound.Len;
-      Rlen : constant Uns32 := R.Typ.Vbound.Len;
+      Llen : constant Uns32 := L.Typ.Abound.Len;
+      Rlen : constant Uns32 := R.Typ.Abound.Len;
       Len : constant Uns32 := Uns32'Max (Llen, Rlen);
       Res : Memtyp;
       Lb, Rb, Carry : Sl_X01;
@@ -405,7 +405,7 @@ package body Synth.Ieee.Numeric_Std is
    function Add_Vec_Int
      (L : Memtyp; R : Uns64; Signed : Boolean; Loc : Syn_Src) return Memtyp
    is
-      Len          : constant Uns32 := L.Typ.Vbound.Len;
+      Len          : constant Uns32 := L.Typ.Abound.Len;
       Res : Memtyp;
       V : Uns64;
       Lb, Rb, Carry : Sl_X01;
@@ -450,8 +450,8 @@ package body Synth.Ieee.Numeric_Std is
    function Sub_Vec_Vec (L, R : Memtyp; Signed : Boolean; Loc : Syn_Src)
                          return Memtyp
    is
-      Llen          : constant Uns32 := L.Typ.Vbound.Len;
-      Rlen          : constant Uns32 := R.Typ.Vbound.Len;
+      Llen          : constant Uns32 := L.Typ.Abound.Len;
+      Rlen          : constant Uns32 := R.Typ.Abound.Len;
       Len           : constant Uns32 := Uns32'Max (Llen, Rlen);
       Res           : Memtyp;
       Lb, Rb, Carry : Sl_X01;
@@ -512,7 +512,7 @@ package body Synth.Ieee.Numeric_Std is
    function Sub_Vec_Int
      (L : Memtyp; R : Uns64; Signed : Boolean; Loc : Syn_Src) return Memtyp
    is
-      Len           : constant Uns32 := L.Typ.Vbound.Len;
+      Len           : constant Uns32 := L.Typ.Abound.Len;
       Res           : Memtyp;
       V             : Uns64;
       Lb, Rb, Carry : Sl_X01;
@@ -557,8 +557,8 @@ package body Synth.Ieee.Numeric_Std is
 
    function Mul_Uns_Uns (L, R : Memtyp; Loc : Syn_Src) return Memtyp
    is
-      Llen          : constant Uns32 := L.Typ.Vbound.Len;
-      Rlen          : constant Uns32 := R.Typ.Vbound.Len;
+      Llen          : constant Uns32 := L.Typ.Abound.Len;
+      Rlen          : constant Uns32 := R.Typ.Abound.Len;
       Len           : constant Uns32 := Llen + Rlen;
       Res           : Memtyp;
       Lb, Rb, Vb, Carry : Sl_X01;
@@ -601,7 +601,7 @@ package body Synth.Ieee.Numeric_Std is
 
    function To_Unsigned (Val : Uns64; Vtyp : Type_Acc) return Memtyp
    is
-      Vlen : constant Uns32 := Vtyp.Vbound.Len;
+      Vlen : constant Uns32 := Vtyp.Abound.Len;
       Res  : Memtyp;
       E    : Std_Ulogic;
    begin
@@ -621,7 +621,7 @@ package body Synth.Ieee.Numeric_Std is
    is
       Lv : Memtyp;
    begin
-      if R.Typ.Vbound.Len = 0 then
+      if R.Typ.Abound.Len = 0 then
          return Create_Memory (R.Typ); --  FIXME: typ
       end if;
       Lv := To_Unsigned (L, R.Typ);
@@ -632,7 +632,7 @@ package body Synth.Ieee.Numeric_Std is
    is
       Rv : Memtyp;
    begin
-      if L.Typ.Vbound.Len = 0 then
+      if L.Typ.Abound.Len = 0 then
          return Create_Memory (L.Typ); --  FIXME: typ
       end if;
       Rv := To_Unsigned (R, L.Typ);
@@ -641,8 +641,8 @@ package body Synth.Ieee.Numeric_Std is
 
    function Mul_Sgn_Sgn (L, R : Memtyp; Loc : Syn_Src) return Memtyp
    is
-      Llen          : constant Uns32 := L.Typ.Vbound.Len;
-      Rlen          : constant Uns32 := R.Typ.Vbound.Len;
+      Llen          : constant Uns32 := L.Typ.Abound.Len;
+      Rlen          : constant Uns32 := R.Typ.Abound.Len;
       Len           : constant Uns32 := Llen + Rlen;
       Res           : Memtyp;
       Lb, Rb, Vb, Carry : Sl_X01;
@@ -703,7 +703,7 @@ package body Synth.Ieee.Numeric_Std is
 
    function To_Signed (Val : Int64; Vtyp : Type_Acc) return Memtyp
    is
-      Vlen : constant Uns32 := Vtyp.Vbound.Len;
+      Vlen : constant Uns32 := Vtyp.Abound.Len;
       Uval : constant Uns64 := To_Uns64 (Val);
       Res  : Memtyp;
       E    : Std_Ulogic;
@@ -724,7 +724,7 @@ package body Synth.Ieee.Numeric_Std is
    is
       Lv : Memtyp;
    begin
-      if R.Typ.Vbound.Len = 0 then
+      if R.Typ.Abound.Len = 0 then
          return Create_Memory (R.Typ); --  FIXME: typ
       end if;
       Lv := To_Signed (L, R.Typ);
@@ -735,7 +735,7 @@ package body Synth.Ieee.Numeric_Std is
    is
       Rv : Memtyp;
    begin
-      if L.Typ.Vbound.Len = 0 then
+      if L.Typ.Abound.Len = 0 then
          return Create_Memory (L.Typ); --  FIXME: typ
       end if;
       Rv := To_Signed (R, L.Typ);
@@ -745,7 +745,7 @@ package body Synth.Ieee.Numeric_Std is
    --  Note: SRC = DST is allowed.
    procedure Neg_Vec (Src : Memory_Ptr; Dst : Memory_Ptr; Typ : Type_Acc)
    is
-      Len : constant Uns32 := Typ.Vbound.Len;
+      Len : constant Uns32 := Typ.Abound.Len;
       Vb, Carry : Sl_X01;
    begin
       Carry := '1';
@@ -774,7 +774,7 @@ package body Synth.Ieee.Numeric_Std is
 
    function Neg_Vec (V : Memtyp; Loc : Syn_Src) return Memtyp
    is
-      Len : constant Uns32 := V.Typ.Vbound.Len;
+      Len : constant Uns32 := V.Typ.Abound.Len;
       Res : Memtyp;
    begin
       Res.Typ := Create_Res_Type (V.Typ, Len);
@@ -811,7 +811,7 @@ package body Synth.Ieee.Numeric_Std is
    function Abs_Vec (V : Memtyp; Loc : Syn_Src) return Memtyp
    is
       pragma Unreferenced (Loc);
-      Len : constant Uns32 := V.Typ.Vbound.Len;
+      Len : constant Uns32 := V.Typ.Abound.Len;
       Res : Memtyp;
       Msb : Sl_X01;
    begin
@@ -916,11 +916,11 @@ package body Synth.Ieee.Numeric_Std is
 
    procedure Divmod (Num, Dem : Memtyp; Quot, Remain : Memtyp)
    is
-      Nlen  : constant Uns32 := Num.Typ.Vbound.Len;
-      Dlen  : constant Uns32 := Dem.Typ.Vbound.Len;
+      Nlen  : constant Uns32 := Num.Typ.Abound.Len;
+      Dlen  : constant Uns32 := Dem.Typ.Abound.Len;
       pragma Assert (Nlen > 0);
       pragma Assert (Dlen > 0);
-      pragma Assert (Quot.Typ.Vbound.Len = Nlen);
+      pragma Assert (Quot.Typ.Abound.Len = Nlen);
       Reg   : Std_Logic_Vector_Type (0 .. Dlen);
       Sub   : Std_Logic_Vector_Type (0 .. Dlen - 1);
       Carry : Sl_X01;
@@ -951,7 +951,7 @@ package body Synth.Ieee.Numeric_Std is
          end if;
       end loop;
       if Remain /= Null_Memtyp then
-         pragma Assert (Remain.Typ.Vbound.Len = Dlen);
+         pragma Assert (Remain.Typ.Abound.Len = Dlen);
          for I in 0 .. Dlen - 1 loop
             Write_Std_Logic (Remain.Mem, I, Reg (I + 1));
          end loop;
@@ -963,7 +963,7 @@ package body Synth.Ieee.Numeric_Std is
       Res : Sl_X01 := '0';
       E : Sl_X01;
    begin
-      for I in 0 .. V.Typ.Vbound.Len - 1 loop
+      for I in 0 .. V.Typ.Abound.Len - 1 loop
          E := To_X01 (Read_Std_Logic (V.Mem, I));
          if E = 'X' then
             return 'X';
@@ -976,8 +976,8 @@ package body Synth.Ieee.Numeric_Std is
 
    function Div_Uns_Uns (L, R : Memtyp; Loc : Syn_Src) return Memtyp
    is
-      Nlen  : constant Uns32 := L.Typ.Vbound.Len;
-      Dlen  : constant Uns32 := R.Typ.Vbound.Len;
+      Nlen  : constant Uns32 := L.Typ.Abound.Len;
+      Dlen  : constant Uns32 := R.Typ.Abound.Len;
       Quot  : Memtyp;
       R0    : Sl_X01;
    begin
@@ -1005,8 +1005,8 @@ package body Synth.Ieee.Numeric_Std is
 
    function Div_Sgn_Sgn (L, R : Memtyp; Loc : Syn_Src) return Memtyp
    is
-      Nlen  : constant Uns32 := L.Typ.Vbound.Len;
-      Dlen  : constant Uns32 := R.Typ.Vbound.Len;
+      Nlen  : constant Uns32 := L.Typ.Abound.Len;
+      Dlen  : constant Uns32 := R.Typ.Abound.Len;
       Quot  : Memtyp;
       R0    : Sl_X01;
       Lu    : Memtyp;
diff --git a/src/synth/synth-vhdl_environment.adb b/src/synth/synth-vhdl_environment.adb
index c7f7daccc..711673fda 100644
--- a/src/synth/synth-vhdl_environment.adb
+++ b/src/synth/synth-vhdl_environment.adb
@@ -124,7 +124,7 @@ package body Synth.Vhdl_Environment is
                Info_Msg_Synth
                  (+Loc,
                   "  " & Prefix
-                    & "(" & Info_Subrange_Vhdl (Off, Wd, Typ.Vbound) & ")");
+                    & "(" & Info_Subrange_Vhdl (Off, Wd, Typ.Abound) & ")");
             end if;
          when Type_Slice
             | Type_Array =>
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb
index beb6883ec..7b1bd91d9 100644
--- a/src/synth/synth-vhdl_eval.adb
+++ b/src/synth/synth-vhdl_eval.adb
@@ -53,14 +53,14 @@ package body Synth.Vhdl_Eval is
 
    function Create_Res_Bound (Prev : Type_Acc) return Type_Acc is
    begin
-      if Prev.Vbound.Dir = Dir_Downto
-        and then Prev.Vbound.Right = 0
+      if Prev.Abound.Dir = Dir_Downto
+        and then Prev.Abound.Right = 0
       then
          --  Normalized range
          return Prev;
       end if;
 
-      return Create_Vec_Type_By_Length (Prev.W, Prev.Vec_El);
+      return Create_Vec_Type_By_Length (Prev.W, Prev.Arr_El);
    end Create_Res_Bound;
 
    function Eval_Vector_Dyadic (Left, Right : Memtyp;
@@ -686,7 +686,7 @@ package body Synth.Vhdl_Eval is
    function Eval_Vector_Reduce
      (Init : Std_Ulogic; Vec : Memtyp; Op : Table_2d) return Memtyp
    is
-      El_Typ : constant Type_Acc := Vec.Typ.Vec_El;
+      El_Typ : constant Type_Acc := Vec.Typ.Arr_El;
       Res : Std_Ulogic;
    begin
       Res := Init;
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index 44cb0c781..f9333b5d6 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -315,7 +315,7 @@ package body Synth.Vhdl_Expr is
                --  In memory MEM, bits are stored from left to right, so in
                --  big endian (MSB is written at offset 0, LSB at
                --  offset VLEN - 1).  Need to reverse: LSB is read first.
-               case Typ.Vec_El.Kind is
+               case Typ.Arr_El.Kind is
                   when Type_Bit =>
                      --  TODO: optimize off mod 32 = 0.
                      for I in Off .. Len - 1 loop
diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb
index 13ebed7f1..bf487ad0c 100644
--- a/src/synth/synth-vhdl_insts.adb
+++ b/src/synth/synth-vhdl_insts.adb
@@ -186,7 +186,7 @@ package body Synth.Vhdl_Insts is
    begin
       case Typ.Kind is
          when Type_Vector =>
-            Hash_Bound (C, Typ.Vbound);
+            Hash_Bound (C, Typ.Abound);
          when Type_Array =>
             declare
                T : Type_Acc;
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb
index 5326f72a0..fba3b3ad5 100644
--- a/src/synth/synth-vhdl_oper.adb
+++ b/src/synth/synth-vhdl_oper.adb
@@ -143,13 +143,13 @@ package body Synth.Vhdl_Oper is
 
       case Res.Kind is
          when Type_Vector =>
-            if Res.Vbound.Dir = Dir_Downto
-              and then Res.Vbound.Right = 0
+            if Res.Abound.Dir = Dir_Downto
+              and then Res.Abound.Right = 0
             then
                --  Normalized range
                return Res;
             end if;
-            return Create_Vec_Type_By_Length (Res.W, Res.Vec_El);
+            return Create_Vec_Type_By_Length (Res.W, Res.Arr_El);
 
          when Type_Slice =>
             return Create_Vec_Type_By_Length (Res.W, Res.Slice_El);
@@ -263,9 +263,9 @@ package body Synth.Vhdl_Oper is
    begin
       --  Note: LEFT or RIGHT can be a single bit.
       if Left.Typ.Kind = Type_Vector then
-         El_Typ := Left.Typ.Vec_El;
+         El_Typ := Left.Typ.Arr_El;
       elsif Right.Typ.Kind = Type_Vector then
-         El_Typ := Right.Typ.Vec_El;
+         El_Typ := Right.Typ.Arr_El;
       else
          raise Internal_Error;
       end if;
@@ -635,7 +635,7 @@ package body Synth.Vhdl_Oper is
             when Oper_Right =>
                Res_Typ := Right.Typ;
          end case;
-         Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Vec_El);
+         Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Arr_El);
          N := Build_Dyadic (Ctxt, Id, L1, R1);
          Set_Location (N, Expr);
          N := Build2_Uresize (Ctxt, N, Res_Typ.W, Get_Location (Expr));
@@ -658,7 +658,7 @@ package body Synth.Vhdl_Oper is
             when Oper_Right =>
                Res_Typ := Right.Typ;
          end case;
-         Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Vec_El);
+         Res_Typ := Create_Vec_Type_By_Length (Res_Typ.W, Res_Typ.Arr_El);
          N := Build_Dyadic (Ctxt, Id, L1, R1);
          Set_Location (N, Expr);
          N := Build2_Sresize (Ctxt, N, Res_Typ.W, Get_Location (Expr));
@@ -1670,7 +1670,7 @@ package body Synth.Vhdl_Oper is
             N := Build_Monadic (Ctxt, Id_Not, N);
             Set_Location (N, Loc);
          end if;
-         return Create_Value_Net (N, Operand.Typ.Vec_El);
+         return Create_Value_Net (N, Operand.Typ.Arr_El);
       end Synth_Vec_Reduce_Monadic;
    begin
       Operand := Synth_Expression_With_Type (Syn_Inst, Operand_Expr, Oper_Typ);
@@ -1788,7 +1788,7 @@ package body Synth.Vhdl_Oper is
                             Expr        : Node) return Valtyp
    is
       pragma Assert (Left.Typ.Kind = Type_Vector);
-      Len : constant Uns32 := Left.Typ.Vbound.Len;
+      Len : constant Uns32 := Left.Typ.Abound.Len;
       Max : Int32;
       Rng : Discrete_Range_Type;
       W   : Uns32;
@@ -1804,7 +1804,7 @@ package body Synth.Vhdl_Oper is
       --  The intermediate result is computed using the least number of bits,
       --  which must represent all positive values in the bounds using a
       --  signed word (so that -1 is also represented).
-      Max := Int32'Max (Left.Typ.Vbound.Left, Left.Typ.Vbound.Right);
+      Max := Int32'Max (Left.Typ.Abound.Left, Left.Typ.Abound.Right);
       W := Netlists.Utils.Clog2 (Uns32 (Max)) + 1;
       Rng := (Dir => Dir_To,
               Is_Signed => True,
@@ -1824,17 +1824,17 @@ package body Synth.Vhdl_Oper is
             if Leftmost then
                --  Iterate from the right to the left.
                Pos := I;
-               if Left.Typ.Vbound.Dir = Dir_To then
-                  V := Int64 (Left.Typ.Vbound.Right) - Int64 (I);
+               if Left.Typ.Abound.Dir = Dir_To then
+                  V := Int64 (Left.Typ.Abound.Right) - Int64 (I);
                else
-                  V := Int64 (Left.Typ.Vbound.Right) + Int64 (I);
+                  V := Int64 (Left.Typ.Abound.Right) + Int64 (I);
                end if;
             else
                Pos := Len - I - 1;
-               if Left.Typ.Vbound.Dir = Dir_To then
-                  V := Int64 (Left.Typ.Vbound.Left) + Int64 (I);
+               if Left.Typ.Abound.Dir = Dir_To then
+                  V := Int64 (Left.Typ.Abound.Left) + Int64 (I);
                else
-                  V := Int64 (Left.Typ.Vbound.Left) - Int64 (I);
+                  V := Int64 (Left.Typ.Abound.Left) - Int64 (I);
                end if;
             end if;
             Sel := Build2_Compare (Ctxt, Id_Eq,
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index 14302134d..02405dd25 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -858,8 +858,8 @@ package body Synth.Vhdl_Stmts is
          when Type_Discrete =>
             return False;
          when Type_Vector =>
-            if V.Typ.Vec_El = Logic_Type then
-               for I in 1 .. Size_Type (V.Typ.Vbound.Len) loop
+            if V.Typ.Arr_El = Logic_Type then
+               for I in 1 .. Size_Type (V.Typ.Abound.Len) loop
                   if Ignore_Choice_Logic (Read_U8 (V.Val.Mem + (I - 1)), Loc)
                   then
                      return True;