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* synth: remove insert gate.Tristan Gingold2019-08-314-70/+0
* synth: improve synth_uresize.Tristan Gingold2019-08-313-26/+50
* synth: elab subprogram interfaces subtypeTristan Gingold2019-08-311-2/+13
* [PATCH] synth-environment: fix thinkos.Tristan Gingold2019-08-311-14/+57
* synth: add physical division (#904)tgingold2019-08-301-1/+11
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| * synth: added division of physical typeMartin Doerfelt2019-08-301-1/+11
* | synth: add support for --synth on llvm, link with -lm.Tristan Gingold2019-08-301-0/+4
* | synth: fix type elaboration of interfaces.Tristan Gingold2019-08-301-2/+0
* | synth: remove unused const gates.Tristan Gingold2019-08-302-13/+5
* | synth: ignore report statement.Tristan Gingold2019-08-301-0/+2
* | vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-301-0/+2
* | synth: handle enumeration subtype in ranges.Tristan Gingold2019-08-301-1/+2
* | synth: fix named association in record aggregate.Tristan Gingold2019-08-301-1/+3
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* synth: add support for record types.Tristan Gingold2019-08-2912-82/+357
* synth: Integer operators (#902)marph912019-08-281-0/+16
* synth: support sequential conditional signal assignment.Tristan Gingold2019-08-271-0/+2
* synth: rework partial assignmentsTristan Gingold2019-08-2710-182/+608
* netlists-disp_vhdl: do not used literals for prefixes.Tristan Gingold2019-08-271-12/+53
* synth: add support for constant exponentiation.Tristan Gingold2019-08-201-0/+10
* synth: set name to assert/assume gates.Tristan Gingold2019-08-204-12/+44
* netlist: fix minor pasto.Tristan Gingold2019-08-201-1/+1
* initial support for reduce and/or (#900)Pepijn de Vos2019-08-203-1/+30
* vhdl: handle assume in verification units.Tristan Gingold2019-08-201-0/+2
* synth: set location on assume/assert gates.Tristan Gingold2019-08-203-8/+19
* synth: handle verification units.Tristan Gingold2019-08-203-2/+37
* synth: handle array attribute "length" (#895)marph912019-08-191-0/+10
* synth: fix tgingold/ghdlsynth#34 (association).Tristan Gingold2019-08-171-2/+1
* synth: handle integer values in subtype conversion.Tristan Gingold2019-08-161-0/+2
* synth: handle integers for displaying vhdl ports.Tristan Gingold2019-08-161-0/+10
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-0/+2
* synth: handle array attributes; handle integer subtypes in generics.Tristan Gingold2019-08-162-2/+91
* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-152-4/+35
* synth: fix handling of assume/assert.Tristan Gingold2019-08-141-6/+65
* ghdlsynth: declare init_for_ghdl_synth.Tristan Gingold2019-08-141-1/+4
* vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.Tristan Gingold2019-08-141-0/+3
* synth: also extract edge in PSL expressions.Tristan Gingold2019-08-133-18/+36
* synth: extract edge for PSL clocks.Tristan Gingold2019-08-131-27/+34
* libghdlsynth: make it almost empty, as libghdl will be used instead.Tristan Gingold2019-08-131-8/+0
* Support for PSL assert and assume in synthesis (#892)Pepijn de Vos2019-08-131-4/+53
* libghdl: also add synthesis part. For #884Tristan Gingold2019-08-133-44/+4
* synth: build_header was replaced by a Makefile target.Tristan Gingold2019-08-131-8/+0
* synth: add comments.Tristan Gingold2019-08-091-1/+9
* synth: fix crash when assignment target is an aggregate.Tristan Gingold2019-08-081-5/+7
* synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.Tristan Gingold2019-08-082-4/+13
* synth: improve support of vhdl08. Fix #882Tristan Gingold2019-08-051-4/+13
* synth: add asserts in synth-valuesTristan Gingold2019-08-051-0/+5
* synth: handle subtype conversions.Tristan Gingold2019-08-055-73/+154
* synth: handle signed conversions in disp_vhdl.Tristan Gingold2019-08-051-2/+6
* synth: preliminary support of integer literals.Tristan Gingold2019-08-022-18/+67
* synth: add a debug procedure.Tristan Gingold2019-08-022-0/+22
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