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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-27 13:55:57 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-27 13:55:57 +0200 |
| commit | 4870e051898d752407da802d4297d1f83bfbe433 (patch) | |
| tree | 41a5e01ce5bf619d23dc15377dee0605670efde7 /src/synth | |
| parent | 26c13e748d27454a43ea1c341570b48a40cd2067 (diff) | |
| download | ghdl-4870e051898d752407da802d4297d1f83bfbe433.tar.gz ghdl-4870e051898d752407da802d4297d1f83bfbe433.tar.bz2 ghdl-4870e051898d752407da802d4297d1f83bfbe433.zip | |
synth: support sequential conditional signal assignment.
Fix tgingold/ghdlsynth-beta#40
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-stmts.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index f37b1388e..b16952d17 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1144,6 +1144,8 @@ package body Synth.Stmts is Synth_If_Statement (Syn_Inst, Stmt); when Iir_Kind_Simple_Signal_Assignment_Statement => Synth_Simple_Signal_Assignment (Syn_Inst, Stmt); + when Iir_Kind_Conditional_Signal_Assignment_Statement => + Synth_Conditional_Signal_Assignment (Syn_Inst, Stmt); when Iir_Kind_Variable_Assignment_Statement => Synth_Variable_Assignment (Syn_Inst, Stmt); when Iir_Kind_Case_Statement => |