iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	vhdl: handle cover and restrict within vunit.	Tristan Gingold	2019-10-15	1	-0/+2
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*	synth: handle overflow literal.	Tristan Gingold	2019-10-15	1	-0/+9
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*	netlists: declare memory gates.	Tristan Gingold	2019-10-15	3	-3/+215
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*	synth-expr: handle any discrete_range in aggregate choices.	Tristan Gingold	2019-10-15	1	-1/+2
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*	synth-insts: accept architecture instantiation in synth_dependencies.	Tristan Gingold	2019-10-15	1	-2/+3
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*	synth-inference: handle multiple connections.	Tristan Gingold	2019-10-14	1	-14/+31
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*	synth-infere: extract clock from and tree.	Tristan Gingold	2019-10-14	1	-17/+102
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*	netlists-dump: do not print name of anonymous parameters.	Tristan Gingold	2019-10-14	1	-2/+6
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*	synth-infere: fix partial assignment with clock enable.	Tristan Gingold	2019-10-14	1	-2/+9
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*	synth: handle constants for condition operator.	Tristan Gingold	2019-10-13	3	-1/+20
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*	synth-stmts: fix thinko (need to adjust type for indexed a 1-bit array).	Tristan Gingold	2019-10-13	1	-2/+5
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*	synth-stmts: handle const indexed array.	Tristan Gingold	2019-10-13	1	-0/+5
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*	synth-oper: handle const array array concat.	Tristan Gingold	2019-10-13	1	-16/+41
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*	synth-oper: add more operations (float div, less for arrays)	Tristan Gingold	2019-10-13	1	-7/+39
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*	synth-stmts: improve support for associations in function calls.	Tristan Gingold	2019-10-13	1	-19/+92
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*	synth-inst: minor refactoring.	Tristan Gingold	2019-10-13	1	-3/+2
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*	synth-oper: handle unsigned unsigned mul.	Tristan Gingold	2019-10-13	1	-0/+13
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*	synth-expr: handle integer type conversion.	Tristan Gingold	2019-10-13	1	-1/+4
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*	synth-expr: handle range array attribute in slices.	Tristan Gingold	2019-10-13	1	-42/+74
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*	vhdl: recognize std_logic_unsigned.conv_integer.	Tristan Gingold	2019-10-13	1	-2/+5
\| \| \| \|	Handle more operators in synth.
*	netlists-iterators: avoid a crash if no ports.	Tristan Gingold	2019-10-13	1	-3/+1
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*	netlists-dump: improve output.	Tristan Gingold	2019-10-13	1	-9/+28
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*	netlists-builders: adjust names of dyn_extract ports.	Tristan Gingold	2019-10-13	1	-2/+2
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*	Show error on wait without condition (#976)	Pepijn de Vos	2019-10-13	1	-0/+4
\| \| \| \| \| \|	* Show error on wait without condition * Null node
*	add record (in)equality (#975)	Pepijn de Vos	2019-10-13	1	-2/+4
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*	vhdl: recognize conv_integer functions from std_logic_arith.	Tristan Gingold	2019-10-11	1	-1/+2
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*	vhdl: recognize std_logic_signed package (from synopsys).	Tristan Gingold	2019-10-11	1	-1/+2
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*	vhdl: recognize minus from std_logic_unsigned	Tristan Gingold	2019-10-11	1	-1/+2
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*	synth: remove synth-types	Tristan Gingold	2019-10-10	4	-91/+13
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*	netlists: add internings child package.	Tristan Gingold	2019-10-10	3	-14/+61
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*	netlists-disp_vhdl: fix pasto on id_asr.	Tristan Gingold	2019-10-10	1	-5/+5
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*	synth: handle constants for enum equality.	Tristan Gingold	2019-10-10	1	-1/+5
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*	netlists: give a name to the free module.	Tristan Gingold	2019-10-10	1	-2/+4
\| \| \| \|	In order to avoid crashes in dumps.
*	synth: rewrite cleanup pass.	Tristan Gingold	2019-10-10	7	-68/+188
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*	synth-decls: ignore use clauses.	Tristan Gingold	2019-10-10	1	-0/+2
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*	synth-opeer: extend synth_uresize	Tristan Gingold	2019-10-10	1	-1/+1
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*	synth-oper: handle more operators.	Tristan Gingold	2019-10-10	1	-3/+6
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*	synth: set name on generate statements.	Tristan Gingold	2019-10-09	2	-6/+16
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*	synth: set location on instances.	Tristan Gingold	2019-10-09	1	-0/+1
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*	synth: use synth.source for setting location.	Tristan Gingold	2019-10-09	8	-17/+34
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*	netlists-disp_vhdl: handle const_SB32	Tristan Gingold	2019-10-09	1	-1/+2
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*	synth-environment: fix a thinko.	Tristan Gingold	2019-10-09	1	-1/+2
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*	synth: improve support of procedure calls.	Tristan Gingold	2019-10-08	1	-20/+25
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*	synth: handle read-only aliases. Fix #973	Tristan Gingold	2019-10-08	1	-1/+9
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*	synth-context: fix encoding of discrete in aggregate	Tristan Gingold	2019-10-08	1	-1/+1
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*	synth-disp_vhdl: fix incorrect code for record of width	Tristan Gingold	2019-10-08	1	-1/+3
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*	synth: fix mul sgn sgn width.	Tristan Gingold	2019-10-08	2	-8/+9
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*	synth: fix incorrect order for concat.	Tristan Gingold	2019-10-08	2	-3/+6
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*	synth-disp_vhdl: handle array/record of 1 element.	Tristan Gingold	2019-10-08	1	-3/+11
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*	synth: handle subprograms in package body.	Tristan Gingold	2019-10-08	1	-0/+5
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