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synth
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Author
Age
Files
Lines
*
vhdl: move annotations from simul to vhdl.
Tristan Gingold
2019-06-29
6
-6
/
+6
*
synth: disp_vhdl: merge literals.
Tristan Gingold
2019-06-28
4
-88
/
+154
*
synth: Move get_input_net to netlists.utils.
Tristan Gingold
2019-06-28
6
-8
/
+9
*
synth: fix disp_vhdl. Can now be analyzed.
Tristan Gingold
2019-06-28
1
-68
/
+159
*
synth: handle some functions from math_real.
Tristan Gingold
2019-06-28
1
-1
/
+43
*
synth: disp_vhdl: handle mux2
Tristan Gingold
2019-06-28
2
-3
/
+32
*
synth: add get_input_net helper.
Tristan Gingold
2019-06-28
7
-19
/
+32
*
synth: disp_vhdl: add disp_template.
Tristan Gingold
2019-06-28
1
-23
/
+46
*
synth: improve disp_vhdl.
Tristan Gingold
2019-06-28
1
-80
/
+232
*
synth: add syn_extract for dynamic slices.
Tristan Gingold
2019-06-28
6
-63
/
+273
*
synth: handle slice assignment.
Tristan Gingold
2019-06-25
5
-31
/
+71
*
synth: add insert gate.
Tristan Gingold
2019-06-24
6
-16
/
+110
*
synth: handle discrete choice in case statements.
Tristan Gingold
2019-06-23
1
-1
/
+5
*
synth: handle more operators.
Tristan Gingold
2019-06-23
2
-12
/
+18
*
synth: remove unused Value_Logic.
Tristan Gingold
2019-06-23
4
-38
/
+5
*
synth: handle ult comparison.
Tristan Gingold
2019-06-23
2
-28
/
+39
*
synth: handle more predefined functions.
Tristan Gingold
2019-06-23
5
-26
/
+115
*
synth-stmts: fix for unordered choices in case statement.
Tristan Gingold
2019-06-23
1
-5
/
+14
*
synth-stmts: handle constant if statements.
Tristan Gingold
2019-06-23
1
-2
/
+18
*
synth-expr: clarify error message.
Tristan Gingold
2019-06-20
1
-2
/
+7
*
synth: get rid of execution and elaboration.
Tristan Gingold
2019-06-19
11
-569
/
+1229
*
synth-expr: use Node instead of Iir (renaming).
Tristan Gingold
2019-06-13
2
-34
/
+34
*
synth-stmts: handle enumeration type in case, renaming.
Tristan Gingold
2019-06-13
2
-64
/
+73
*
synth-expr: handle choice_by_expression in aggregates.
Tristan Gingold
2019-06-12
1
-3
/
+30
*
synth: handle enumerated types.
Tristan Gingold
2019-06-12
5
-51
/
+97
*
synth-expr: resize for uns-uns operations.
Tristan Gingold
2019-06-12
1
-18
/
+28
*
netlist-disp_vhdl: display parameters, fix output
Tristan Gingold
2019-06-12
1
-11
/
+45
*
synth: handle conditional generate process.
Tristan Gingold
2019-06-11
1
-1
/
+45
*
synth: support conditional signal assignments.
Tristan Gingold
2019-06-08
7
-9
/
+79
*
synth: handle integer +/- for constants.
Tristan Gingold
2019-06-08
2
-21
/
+39
*
synth: WIP for dependencies.
Tristan Gingold
2019-06-07
3
-11
/
+74
*
synth: add comments.
Tristan Gingold
2019-06-07
2
-5
/
+13
*
synth: add comments and refactoring.
Tristan Gingold
2019-06-07
9
-25
/
+45
*
synth: ignore attribute specifications
Christos Gentsos
2019-06-06
1
-0
/
+2
*
synth: handle numeric_std unsigned - unsigned add and sub
Christos Gentsos
2019-06-06
1
-0
/
+22
*
synth: handle array equality op (just for arrays of identical range)
Christos Gentsos
2019-06-06
1
-0
/
+8
*
synth: enabled vector AND, OR and XOR
Christos Gentsos
2019-06-06
1
-8
/
+14
*
synth: added support for numeric_std unary negation
Christos Gentsos
2019-06-06
2
-0
/
+5
*
synth: handle numeric_std subtraction (addition was already there)
Christos Gentsos
2019-06-06
1
-0
/
+11
*
synth: added support for vector "not" operation
Christos Gentsos
2019-06-06
1
-0
/
+9
*
synth: added support for array-element and element-array concats
Christos Gentsos
2019-06-06
1
-2
/
+27
*
synth-decls: ignore attribute declarations
Christos Gentsos
2019-06-06
1
-0
/
+2
*
synth-expr: fix a crash in vectorize_array
Tristan Gingold
2019-06-06
1
-1
/
+4
*
libghdlsynth: fix startup crash.
Tristan Gingold
2019-06-06
1
-0
/
+2
*
synth: add support for constants.
Pepijn de Vos
2019-05-28
2
-1
/
+9
*
synth: use only one edge gate, make it fully abstract. Handle falling_edge.
Tristan Gingold
2019-05-22
5
-35
/
+34
*
synth: add disp_vhdl.
Tristan Gingold
2019-05-21
2
-0
/
+262
*
vhdl: decouple errorouts a bit more.
Tristan Gingold
2019-05-10
1
-2
/
+2
*
vhdl: extract vhdl.errors from errorout.
Tristan Gingold
2019-05-08
6
-5
/
+6
*
vhdl: move iirs_utils to vhdl.utils
Tristan Gingold
2019-05-06
4
-5
/
+5
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