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* vhdl: move annotations from simul to vhdl.Tristan Gingold2019-06-296-6/+6
* synth: disp_vhdl: merge literals.Tristan Gingold2019-06-284-88/+154
* synth: Move get_input_net to netlists.utils.Tristan Gingold2019-06-286-8/+9
* synth: fix disp_vhdl. Can now be analyzed.Tristan Gingold2019-06-281-68/+159
* synth: handle some functions from math_real.Tristan Gingold2019-06-281-1/+43
* synth: disp_vhdl: handle mux2Tristan Gingold2019-06-282-3/+32
* synth: add get_input_net helper.Tristan Gingold2019-06-287-19/+32
* synth: disp_vhdl: add disp_template.Tristan Gingold2019-06-281-23/+46
* synth: improve disp_vhdl.Tristan Gingold2019-06-281-80/+232
* synth: add syn_extract for dynamic slices.Tristan Gingold2019-06-286-63/+273
* synth: handle slice assignment.Tristan Gingold2019-06-255-31/+71
* synth: add insert gate.Tristan Gingold2019-06-246-16/+110
* synth: handle discrete choice in case statements.Tristan Gingold2019-06-231-1/+5
* synth: handle more operators.Tristan Gingold2019-06-232-12/+18
* synth: remove unused Value_Logic.Tristan Gingold2019-06-234-38/+5
* synth: handle ult comparison.Tristan Gingold2019-06-232-28/+39
* synth: handle more predefined functions.Tristan Gingold2019-06-235-26/+115
* synth-stmts: fix for unordered choices in case statement.Tristan Gingold2019-06-231-5/+14
* synth-stmts: handle constant if statements.Tristan Gingold2019-06-231-2/+18
* synth-expr: clarify error message.Tristan Gingold2019-06-201-2/+7
* synth: get rid of execution and elaboration.Tristan Gingold2019-06-1911-569/+1229
* synth-expr: use Node instead of Iir (renaming).Tristan Gingold2019-06-132-34/+34
* synth-stmts: handle enumeration type in case, renaming.Tristan Gingold2019-06-132-64/+73
* synth-expr: handle choice_by_expression in aggregates.Tristan Gingold2019-06-121-3/+30
* synth: handle enumerated types.Tristan Gingold2019-06-125-51/+97
* synth-expr: resize for uns-uns operations.Tristan Gingold2019-06-121-18/+28
* netlist-disp_vhdl: display parameters, fix outputTristan Gingold2019-06-121-11/+45
* synth: handle conditional generate process.Tristan Gingold2019-06-111-1/+45
* synth: support conditional signal assignments.Tristan Gingold2019-06-087-9/+79
* synth: handle integer +/- for constants.Tristan Gingold2019-06-082-21/+39
* synth: WIP for dependencies.Tristan Gingold2019-06-073-11/+74
* synth: add comments.Tristan Gingold2019-06-072-5/+13
* synth: add comments and refactoring.Tristan Gingold2019-06-079-25/+45
* synth: ignore attribute specificationsChristos Gentsos2019-06-061-0/+2
* synth: handle numeric_std unsigned - unsigned add and subChristos Gentsos2019-06-061-0/+22
* synth: handle array equality op (just for arrays of identical range)Christos Gentsos2019-06-061-0/+8
* synth: enabled vector AND, OR and XORChristos Gentsos2019-06-061-8/+14
* synth: added support for numeric_std unary negationChristos Gentsos2019-06-062-0/+5
* synth: handle numeric_std subtraction (addition was already there)Christos Gentsos2019-06-061-0/+11
* synth: added support for vector "not" operationChristos Gentsos2019-06-061-0/+9
* synth: added support for array-element and element-array concatsChristos Gentsos2019-06-061-2/+27
* synth-decls: ignore attribute declarationsChristos Gentsos2019-06-061-0/+2
* synth-expr: fix a crash in vectorize_arrayTristan Gingold2019-06-061-1/+4
* libghdlsynth: fix startup crash.Tristan Gingold2019-06-061-0/+2
* synth: add support for constants.Pepijn de Vos2019-05-282-1/+9
* synth: use only one edge gate, make it fully abstract. Handle falling_edge.Tristan Gingold2019-05-225-35/+34
* synth: add disp_vhdl.Tristan Gingold2019-05-212-0/+262
* vhdl: decouple errorouts a bit more.Tristan Gingold2019-05-101-2/+2
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-086-5/+6
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-064-5/+5
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