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synth
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Author
Age
Files
Lines
*
vhdl: Iir_Kind_Foreign_Module is now a library unit
Tristan Gingold
2021-11-09
3
-9
/
+14
*
vhdl/psl: handle PSL inherit spec. For #1899
Tristan Gingold
2021-11-05
2
-25
/
+28
*
synth: Support alias declarations in vunit
tmeissner
2021-11-02
3
-5
/
+14
*
synth: do full elaboration before synthesis
Tristan Gingold
2021-11-01
58
-1996
/
+5291
*
synth: reject wait statement. Fix #1903
Tristan Gingold
2021-10-29
1
-0
/
+3
*
synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896
Tristan Gingold
2021-10-18
1
-1
/
+5
*
synth: Support PSL declarations in inline PSL
tmeissner
2021-10-14
1
-1
/
+2
*
synth: add support for sequence instance in vunit. Fix #1889
Tristan Gingold
2021-10-13
1
-2
/
+4
*
synth-vhdl_expr.adb: handle more dynamic slice cases. Fix #1886
Tristan Gingold
2021-10-10
1
-42
/
+74
*
synth-vhdl_expr: fix handling of negative factor in slice. For #1886
Tristan Gingold
2021-10-09
1
-25
/
+61
*
synth-vhdl_decls.adb: also detect unassigned variables.
Tristan Gingold
2021-10-09
1
-11
/
+4
*
netlists-disp_verilog: fix name for memory initialization
Tristan Gingold
2021-09-28
1
-3
/
+4
*
netlists-disp_verilog: fix output of parameter assignments. Fix #1866
Tristan Gingold
2021-09-15
1
-12
/
+12
*
netlists-disp_verilog.adb: add 'parameter' before parameters declaration
Tristan Gingold
2021-09-15
1
-1
/
+1
*
synth/netlists-disp_verilog: fix output of parameter values. For #1866
Tristan Gingold
2021-09-15
3
-12
/
+37
*
vhdl: move Get_Source_Identifier to vhdl-utils
Tristan Gingold
2021-09-15
1
-18
/
+0
*
synth-vhdl_oper: handle nor for boolean
Tristan Gingold
2021-09-14
1
-0
/
+1
*
vhdl-canon: recurse for default block configuration of a vunit.
Tristan Gingold
2021-09-12
1
-7
/
+2
*
synth-vhdl_stmts: fix crash on nested if-generate statement in vunits.
Tristan Gingold
2021-09-11
1
-2
/
+5
*
vhdl: allow constants in vunit declarations. Fix #1856
Tristan Gingold
2021-09-08
1
-0
/
+2
*
netlists-cleanup: avoid crash when keep attribute value is a string
Tristan Gingold
2021-09-07
1
-2
/
+39
*
synth-vhdl_stmts.adb: do not expect configuration for vunit.
Tristan Gingold
2021-09-01
1
-3
/
+3
*
synth: handle PSL async_abort and sync_abort. For #1654
Tristan Gingold
2021-08-31
3
-10
/
+44
*
synth-vhdl_stmts: fix a crash on never triggered PSL assertion.
Tristan Gingold
2021-08-29
1
-0
/
+6
*
synth: improve result of is_positive
Tristan Gingold
2021-08-29
4
-10
/
+15
*
netlists-inference: improve location for dff.
Tristan Gingold
2021-08-29
1
-1
/
+1
*
synth: factorize code to create base instance
Tristan Gingold
2021-08-28
7
-57
/
+104
*
synthesis.adb: abstract instance_passes
Tristan Gingold
2021-08-28
3
-23
/
+34
*
synth-environment: add subprograms for signals (preliminary work)
Tristan Gingold
2021-08-28
2
-5
/
+110
*
synth-memtype: export conversion functions
Tristan Gingold
2021-08-28
2
-7
/
+9
*
synth: add build2_concat2 and use it for vhdl concat.
Tristan Gingold
2021-08-28
3
-4
/
+18
*
ghdlsynth: add debug option for elaboration
Tristan Gingold
2021-08-28
1
-0
/
+3
*
synth-vhdl_decls.adb: add comments
Tristan Gingold
2021-08-28
1
-0
/
+4
*
netlists-disp_verilog: handle initial value for idff and isignal
Tristan Gingold
2021-08-28
1
-8
/
+18
*
synth: do not remove signals with a keep attribute.
Tristan Gingold
2021-08-27
2
-1
/
+31
*
netlists-disp_verilog: fix handling of unconnected port
Tristan Gingold
2021-08-26
1
-3
/
+1
*
synth: reuse signal name while creating memories. Fix #1838
Tristan Gingold
2021-08-25
5
-20
/
+34
*
vhdl: remove iir_kind_anonymous_signal_declaration (now unused)
Tristan Gingold
2021-08-24
4
-19
/
+0
*
vhdl: introduce iir_kind_association_element_by_name
Tristan Gingold
2021-08-06
1
-3
/
+4
*
synth: minor renaming in netlists-memories
Tristan Gingold
2021-06-30
3
-10
/
+11
*
synth-vhdl_context.adb(Is_Full): consider fractional words.
Tristan Gingold
2021-06-23
1
-2
/
+16
*
synth-vhdl_stmts: add location on Addidx
Tristan Gingold
2021-06-21
1
-0
/
+2
*
synth-environment: early transformation of dyn_insert to dyn_insert_en
Tristan Gingold
2021-06-21
4
-25
/
+59
*
synth-vhdl_stmts: merge static extract before dyn_extract.
Tristan Gingold
2021-06-21
1
-4
/
+2
*
synth-vhdl_expr: adjust width of memidx for indexed names.
Tristan Gingold
2021-06-21
1
-1
/
+1
*
synth: add a gate on an optimization to simplify memory handling.
Tristan Gingold
2021-06-17
2
-67
/
+38
*
netlists-memories: strengthen dyn_extract mux reduction. Fix #1781
Tristan Gingold
2021-06-16
2
-1
/
+52
*
synth: minor fixes
Tristan Gingold
2021-06-15
2
-9
/
+8
*
netlists-memories: avoid a crash on uninitialized ROM.
Tristan Gingold
2021-05-24
1
-1
/
+9
*
netlists-disp_verilog: fix display of constants
Tristan Gingold
2021-05-07
1
-10
/
+20
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