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* synth-vhdl_stmts: fix missing newline in default assertion messagesTristan Gingold2022-09-251-3/+3
* synth: handle default expression for IN variables in assocsTristan Gingold2022-09-251-4/+10
* synth: handle selected names in targetsTristan Gingold2022-09-251-1/+2
* synth-vhdl_eval: handle null-null in array concatenationsTristan Gingold2022-09-251-0/+6
* simul: gather disconnection specifications, create guard signalTristan Gingold2022-09-251-3/+3
* synth: ignore groups and group templatesTristan Gingold2022-09-252-0/+12
* synth: handle attribute namesTristan Gingold2022-09-251-13/+16
* synth: handle individual subprogram associations for expressionsTristan Gingold2022-09-251-55/+61
* synth: rework association conversionsTristan Gingold2022-09-252-28/+64
* synth-vhdl_stmts: rework for subprogram associations (WIP)Tristan Gingold2022-09-251-57/+36
* synth-vhdl_stmts: support of individual paramater associations (WIP)Tristan Gingold2022-09-252-106/+238
* synth-vhdl_stmts: refactore synth_subprogram_associationsTristan Gingold2022-09-251-49/+52
* synth-vhdl_stmts: refactoreTristan Gingold2022-09-251-23/+32
* synth-vhdl_stmts: refactoringTristan Gingold2022-09-251-189/+208
* synth-vhdl_stmts: rework in progress of subprogram associationsTristan Gingold2022-09-251-108/+115
* synth-vhdl_insts: move pragma unreferencedTristan Gingold2022-09-211-1/+2
* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-192-51/+3
* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-193-193/+31
* synth: rename vhdl.annotations to elab.vhdl_annotationsTristan Gingold2022-09-196-9/+1708
* synth: rework subprogram associations (WIP)Tristan Gingold2022-09-192-41/+84
* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-183-10/+10
* synth: fix assert failure on attribute specificationTristan Gingold2022-09-181-1/+5
* simul: handle type conversions in port associationsTristan Gingold2022-09-182-38/+40
* synth: handle open variable associationTristan Gingold2022-09-171-22/+31
* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-172-13/+11
* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-174-67/+18
* synth: handle protected types in subprogramsTristan Gingold2022-09-172-7/+50
* synth: improve file handling (skip extra data, errors)Tristan Gingold2022-09-173-3/+53
* synth: finalize filesTristan Gingold2022-09-173-4/+30
* synth: handle read length on text filesTristan Gingold2022-09-171-16/+40
* synth: handle incomplete typesTristan Gingold2022-09-176-24/+87
* synth: handle individual generic associationsTristan Gingold2022-09-171-5/+35
* synth: factorize code with synth_assignment_prefixTristan Gingold2022-09-161-75/+15
* synth: preliminary work to factorize codeTristan Gingold2022-09-165-39/+64
* simul: handle active attributeTristan Gingold2022-09-163-1/+9
* synth: handle val attribute for static bit/logic valuesTristan Gingold2022-09-161-0/+3
* synth: improve handling of complex typesTristan Gingold2022-09-154-8/+30
* synth: handle vhdl-87 filesTristan Gingold2022-09-151-0/+6
* synth: handle access subtypesTristan Gingold2022-09-151-0/+8
* synth: handle read for files of unconstrained arraysTristan Gingold2022-09-153-1/+54
* synth-vhdl_stmts: handle attribute names in expressionsTristan Gingold2022-09-141-1/+3
* synth: detect overflow in static exponentiationTristan Gingold2022-09-141-3/+16
* synth: add bounds check for float-integer type conversionTristan Gingold2022-09-121-2/+21
* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-122-1/+8
* synth: handle succ,pred,leftof,rightof attributesTristan Gingold2022-09-121-0/+95
* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-117-20/+58
* synth: initialize out parameters of proceduresTristan Gingold2022-09-111-2/+9
* synth: fix and add checks for memory management.Tristan Gingold2022-09-1012-110/+328
* simul: add support for protected objectsTristan Gingold2022-09-089-20/+204
* elab-vhdl_objtypes: handle bounded array base type. Fix #2187Tristan Gingold2022-09-081-1/+2
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