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* synth: preliminary support for user packages.Tristan Gingold2019-10-071-84/+5
* ghdlsynth: fix crash when using libghdl.Tristan Gingold2019-10-061-2/+0
* synth: add error messages for latches.Tristan Gingold2019-10-061-0/+2
* synth: add base_instance.Tristan Gingold2019-09-201-8/+6
* synth: rename get/set_module for instances.Tristan Gingold2019-09-201-1/+1
* synth-context: get rid off Set_Block_Scope.Tristan Gingold2019-09-201-3/+1
* synth: refactoring to reduce global variables.Tristan Gingold2019-09-191-13/+8
* synth: make synth_instance_type private.Tristan Gingold2019-09-191-1/+1
* synth-disp_vhdl: handle record for input ports.Tristan Gingold2019-09-031-7/+4
* vhdl: declare verification units (WIP).Tristan Gingold2019-08-161-0/+2
* synth: preliminary support of dynamic indexing.Tristan Gingold2019-07-281-17/+37
* synth_top_entity: pass config + minor cleanup.Tristan Gingold2019-07-111-1/+5
* synth: add synth_top_entity.Tristan Gingold2019-07-101-191/+1
* synth: handle instantiation (WIP)Tristan Gingold2019-07-101-30/+8
* synthesis: add Node instead of Iir.Tristan Gingold2019-07-081-10/+10
* synth: support top-level generics.Tristan Gingold2019-07-061-0/+15
* vhdl: move annotations from simul to vhdl.Tristan Gingold2019-06-291-1/+1
* synth: get rid of execution and elaboration.Tristan Gingold2019-06-191-24/+26
* synth: support conditional signal assignments.Tristan Gingold2019-06-081-2/+4
* synth: WIP for dependencies.Tristan Gingold2019-06-071-0/+57
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
* Create the simul.ads package (for a namespace).Tristan Gingold2017-11-241-2/+2
* simulation: refactoring (move block_instance to iir_values).Tristan Gingold2017-11-241-0/+1
* synth: defer gates removal after at end of entity synthesis.Tristan Gingold2017-02-151-1/+5
* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+261