Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | synth-vhdl_stmts: export Synth_Subprogram_Back_Association | Tristan Gingold | 2022-05-31 | 1 | -0/+5 |
* | synth-vhdl_stmts: export two procedures, adjust assertion message | Tristan Gingold | 2022-05-29 | 1 | -0/+4 |
* | vhdl-canon: add Canon_Add_Suspend_State | Tristan Gingold | 2022-05-26 | 1 | -0/+6 |
* | synth-vhdl_stmts: write generic procedure Assign_Aggregate. | Tristan Gingold | 2022-05-21 | 1 | -0/+13 |
* | synth-vhdl_stmts: export synth_target | Tristan Gingold | 2022-05-12 | 1 | -0/+39 |
* | synth: add a flag to force creation of variables | Tristan Gingold | 2022-05-11 | 1 | -0/+2 |
* | synth: add current_stmt, minor rework | Tristan Gingold | 2022-05-09 | 1 | -0/+14 |
* | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -9/+7 |
* | synth: file renaming for decls, expr, insts and stmts. | Tristan Gingold | 2021-04-28 | 1 | -0/+167 |