| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: remove synth-types | Tristan Gingold | 2019-10-10 | 1 | -28/+0 |
| * | synth: rework range. | Tristan Gingold | 2019-07-26 | 1 | -6/+0 |
| * | synth: preliminary support of integer subtypes. | Tristan Gingold | 2019-07-26 | 1 | -3/+4 |
| * | synth: handle vhdl2008 std_logic_1164, handle anonymous_signal. | Tristan Gingold | 2019-07-04 | 1 | -3/+3 |
| * | synth: add comments and refactoring. | Tristan Gingold | 2019-06-07 | 1 | -1/+1 |
| * | vhdl: rename iirs to vhdl.nodes | Tristan Gingold | 2019-05-05 | 1 | -1/+1 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+33 |
 |
index : iCE40/ghdl | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |