iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: rework range.	Tristan Gingold	2019-07-26	1	-37/+0
*	synth: preliminary support of integer subtypes.	Tristan Gingold	2019-07-26	1	-28/+31
*	synth: handle vhdl2008 std_logic_1164, handle anonymous_signal.	Tristan Gingold	2019-07-04	1	-6/+17
*	vhdl: move annotations from simul to vhdl.	Tristan Gingold	2019-06-29	1	-1/+1
*	synth: get rid of execution and elaboration.	Tristan Gingold	2019-06-19	1	-8/+6
*	synth: handle enumerated types.	Tristan Gingold	2019-06-12	1	-5/+2
*	vhdl: extract vhdl.errors from errorout.	Tristan Gingold	2019-05-08	1	-1/+1
*	vhdl: move iirs_utils to vhdl.utils	Tristan Gingold	2019-05-06	1	-1/+1
*	vhdl: move ieee packages to vhdl children.	Tristan Gingold	2019-05-05	1	-3/+3
*	vhdl: move std_standard package to vhdl child.	Tristan Gingold	2019-05-05	1	-3/+3
*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-3/+3
*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+78