| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: add concat_array function. | Tristan Gingold | 2019-07-04 | 1 | -0/+8 |
| * | synth: add dyn_insert module. | Tristan Gingold | 2019-07-01 | 1 | -1/+1 |
| * | synth: add syn_extract for dynamic slices. | Tristan Gingold | 2019-06-28 | 1 | -1/+5 |
| * | synth: handle slice assignment. | Tristan Gingold | 2019-06-25 | 1 | -0/+5 |
| * | synth: add insert gate. | Tristan Gingold | 2019-06-24 | 1 | -0/+5 |
| * | synth: get rid of execution and elaboration. | Tristan Gingold | 2019-06-19 | 1 | -4/+14 |
| * | synth-expr: use Node instead of Iir (renaming). | Tristan Gingold | 2019-06-13 | 1 | -2/+2 |
| * | synth: add comments and refactoring. | Tristan Gingold | 2019-06-07 | 1 | -0/+1 |
| * | vhdl: rename iirs to vhdl.nodes | Tristan Gingold | 2019-05-05 | 1 | -1/+1 |
| * | synth: improve generation of aggregates. | Tristan Gingold | 2019-04-16 | 1 | -1/+1 |
| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -1/+1 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+42 |
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index : iCE40/ghdl | |
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