| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: refactoring in inference/environment. | Tristan Gingold | 2019-08-01 | 1 | -0/+2 |
| * | synth: refactor inference, add comment, strengthen check. | Tristan Gingold | 2019-08-01 | 1 | -0/+2 |
| * | synth: finalize concurrent assignments (WIP). | Tristan Gingold | 2019-07-19 | 1 | -1/+26 |
| * | synth: make more types private. | Tristan Gingold | 2019-07-17 | 1 | -34/+47 |
| * | synth: make type Wire_Id_Record private. | Tristan Gingold | 2019-07-17 | 1 | -23/+37 |
| * | synth: renaming of Assign to Seq_Assign. | Tristan Gingold | 2019-07-17 | 1 | -14/+15 |
| * | synth: add comments. | Tristan Gingold | 2019-07-17 | 1 | -0/+1 |
| * | synth-environement: add comments. | Tristan Gingold | 2019-07-08 | 1 | -3/+2 |
| * | synth: add comments. | Tristan Gingold | 2019-06-07 | 1 | -3/+6 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+153 |
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index : iCE40/ghdl | |
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