| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: preliminary support of multiport rams (using shared variable). | Tristan Gingold | 2020-03-28 | 1 | -12/+75 |
| | | | | | For #1069 | ||||
| * | synth-environment: fix incorrect memory access. | Tristan Gingold | 2020-03-25 | 1 | -2/+6 |
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| * | synth-environment: simplify code. | Tristan Gingold | 2020-03-25 | 1 | -9/+5 |
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| * | synth: handle reuse of inferred dff in the same process. | Tristan Gingold | 2020-03-22 | 1 | -25/+60 |
| | | | | | Fix tgingold/ghdlsynth-beta#93 | ||||
| * | synth-environment: keep order of seq_assign in phi nodes. | Tristan Gingold | 2020-03-21 | 1 | -5/+11 |
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| * | synth: refactoring inference (WIP). | Tristan Gingold | 2020-03-15 | 1 | -32/+69 |
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| * | synth-environment: handle unassigned outputs. | Tristan Gingold | 2020-02-18 | 1 | -6/+8 |
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| * | synth: rework (again) memory inference. | Tristan Gingold | 2020-02-10 | 1 | -7/+25 |
| | | | | | | | Preliminary work to support multi-clock memories. Strengthen and fix fallout of Check_Connected. Rename synth.inference to netlists.inference. | ||||
| * | synth: improve support of out/inout variable parameters. | Tristan Gingold | 2020-01-08 | 1 | -0/+2 |
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| * | synth-environment: also optimize mux merge for sub-nets. | Tristan Gingold | 2019-12-31 | 1 | -1/+1 |
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| * | synth-environment: fix links and counts in | Tristan Gingold | 2019-11-12 | 1 | -0/+3 |
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| * | synth: merge partial assignments before merging phis. | Tristan Gingold | 2019-11-11 | 1 | -0/+56 |
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| * | synth-decls: handle unassigned signal/object. For issue 65 | Tristan Gingold | 2019-11-07 | 1 | -0/+1 |
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| * | synth: extract netlists-folds from netlists-builders. | Tristan Gingold | 2019-11-05 | 1 | -0/+1 |
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| * | synth: create build2_concat from netlists-concat. | Tristan Gingold | 2019-10-27 | 1 | -0/+1 |
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| * | synth-environment: fix a thinko. | Tristan Gingold | 2019-10-09 | 1 | -1/+2 |
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| * | synth: propagate assignments out of subprograms. Fix #960 | Tristan Gingold | 2019-10-06 | 1 | -0/+27 |
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| * | netlists: remove renaming of Get_Parent for Net. | Tristan Gingold | 2019-10-06 | 1 | -3/+3 |
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| * | synth: add error messages for latches. | Tristan Gingold | 2019-10-06 | 1 | -1/+0 |
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| * | synth: fix extract_merge_partial_assigns. | Tristan Gingold | 2019-10-02 | 1 | -5/+15 |
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| * | synth: fix in extract_merge_partial_assigns. | Tristan Gingold | 2019-10-01 | 1 | -0/+5 |
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| * | synth-environment: optimize cascaded if. | Tristan Gingold | 2019-09-28 | 1 | -1/+27 |
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| * | synth: finalize declarations and free wires. | Tristan Gingold | 2019-09-27 | 1 | -14/+92 |
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| * | synth: improve locations tracking. | Tristan Gingold | 2019-09-18 | 1 | -3/+9 |
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| * | synth: fix to get_current_assign_value. | Tristan Gingold | 2019-09-17 | 1 | -7/+4 |
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| * | synth: fold addition on constant nets. | Tristan Gingold | 2019-09-17 | 1 | -0/+45 |
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| * | synth: improve support of return statement. | Tristan Gingold | 2019-09-11 | 1 | -0/+5 |
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| * | synth: handle partial assignments in case statements. | Tristan Gingold | 2019-09-07 | 1 | -17/+0 |
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| * | synth: abstract of Merge_Assigns. | Tristan Gingold | 2019-09-06 | 1 | -56/+111 |
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| * | synth: add netlists.concats | Tristan Gingold | 2019-09-05 | 1 | -31/+7 |
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| * | [PATCH] synth-environment: fix thinkos. | Tristan Gingold | 2019-08-31 | 1 | -14/+57 |
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| * | synth: add support for record types. | Tristan Gingold | 2019-08-29 | 1 | -4/+0 |
| | | | | | (WIP: need to fix regression of stmt01). | ||||
| * | synth: rework partial assignments | Tristan Gingold | 2019-08-27 | 1 | -130/+488 |
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| * | synth: improve error message for multiple assignments. | Tristan Gingold | 2019-08-02 | 1 | -4/+20 |
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| * | synth: handle partial assignments in a process (WIP). | Tristan Gingold | 2019-08-01 | 1 | -18/+75 |
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| * | synth: refactoring in inference/environment. | Tristan Gingold | 2019-08-01 | 1 | -1/+8 |
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| * | synth: refactor inference, add comment, strengthen check. | Tristan Gingold | 2019-08-01 | 1 | -12/+18 |
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| * | synth: add concatn gate | Tristan Gingold | 2019-07-19 | 1 | -1/+10 |
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| * | synth: finalize concurrent assignments (WIP). | Tristan Gingold | 2019-07-19 | 1 | -23/+274 |
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| * | synth: make type Wire_Id_Record private. | Tristan Gingold | 2019-07-17 | 1 | -0/+29 |
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| * | synth: renaming of Assign to Seq_Assign. | Tristan Gingold | 2019-07-17 | 1 | -50/+52 |
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| * | synth: add comments. | Tristan Gingold | 2019-07-17 | 1 | -0/+1 |
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| * | synth: add comments. | Tristan Gingold | 2019-07-15 | 1 | -6/+10 |
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| * | synth-environement: add comments. | Tristan Gingold | 2019-07-08 | 1 | -0/+3 |
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| * | synth: support async reset in inference. | Tristan Gingold | 2019-04-16 | 1 | -0/+3 |
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| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+334 |
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index : iCE40/ghdl | |
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