iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: rework range.	Tristan Gingold	2019-07-26	1	-4/+2
*	synth: preliminary support of integer subtypes.	Tristan Gingold	2019-07-26	1	-2/+15
*	synth: handle array aggregate.	Tristan Gingold	2019-07-26	1	-1/+1
*	synth: handle bit.	Tristan Gingold	2019-07-25	1	-1/+1
*	synth: make type Wire_Id_Record private.	Tristan Gingold	2019-07-17	1	-11/+0
*	synth: renaming of Assign to Seq_Assign.	Tristan Gingold	2019-07-17	1	-1/+1
*	synth: handle instantiation (WIP)	Tristan Gingold	2019-07-10	1	-3/+16
*	synth: handle simple user function calls.	Tristan Gingold	2019-07-06	1	-0/+1
*	synth: destroy iterator after for-loop.	Tristan Gingold	2019-07-01	1	-1/+16
*	synth: handle more operators.	Tristan Gingold	2019-06-23	1	-8/+3
*	synth: remove unused Value_Logic.	Tristan Gingold	2019-06-23	1	-8/+0
*	synth: get rid of execution and elaboration.	Tristan Gingold	2019-06-19	1	-133/+198
*	synth: handle enumerated types.	Tristan Gingold	2019-06-12	1	-31/+43
*	synth: support conditional signal assignments.	Tristan Gingold	2019-06-08	1	-0/+8
*	vhdl: extract vhdl.errors from errorout.	Tristan Gingold	2019-05-08	1	-1/+1
*	vhdl: move iirs_utils to vhdl.utils	Tristan Gingold	2019-05-06	1	-2/+2
*	vhdl: move ieee packages to vhdl children.	Tristan Gingold	2019-05-05	1	-3/+3
*	vhdl: move std_standard package to vhdl child.	Tristan Gingold	2019-05-05	1	-3/+4
*	simul: replace Get_Instance_For_Slot by Get_Instance_Object.	Tristan Gingold	2017-12-11	1	-3/+3
*	Create the simul.ads package (for a namespace).	Tristan Gingold	2017-11-24	1	-8/+8
*	simulation: refactoring (move block_instance to iir_values).	Tristan Gingold	2017-11-24	1	-1/+0
*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+229