aboutsummaryrefslogtreecommitdiffstats
path: root/src/synth/synth-context.adb
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2019-05-05 08:00:35 +0200
committerTristan Gingold <tgingold@free.fr>2019-05-05 08:05:12 +0200
commit3fa8d9eb8b700044d149bdf12da6cb023568b8c0 (patch)
tree3cbd54423bad53e6db401e43ef0e4216833cd8b9 /src/synth/synth-context.adb
parent85d360929d13e6b0bcb082f144883a43f402ce22 (diff)
downloadghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.tar.gz
ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.tar.bz2
ghdl-3fa8d9eb8b700044d149bdf12da6cb023568b8c0.zip
vhdl: move ieee packages to vhdl children.
Diffstat (limited to 'src/synth/synth-context.adb')
-rw-r--r--src/synth/synth-context.adb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 607c94555..95eb09baa 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -26,7 +26,7 @@ with Errorout; use Errorout;
with Iirs_Utils;
with Vhdl.Std_Package;
-with Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164;
with Simul.Annotations; use Simul.Annotations;
with Simul.Execution;
@@ -90,8 +90,8 @@ package body Synth.Context is
end if;
when Iir_Kind_Array_Type_Definition =>
-- Well known array types.
- if Btype = Ieee.Std_Logic_1164.Std_Logic_Vector_Type
- or else Btype = Ieee.Std_Logic_1164.Std_Ulogic_Vector_Type
+ if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type
+ or else Btype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Vector_Type
then
return Alloc_Wire
(Kind, Obj, Bounds_To_Range (Val.Bounds.D (1)));