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* synth: disp_vhdl: merge literals.Tristan Gingold2019-06-281-0/+15
* synth: Move get_input_net to netlists.utils.Tristan Gingold2019-06-281-0/+5
* synth: defer gates removal after at end of entity synthesis.Tristan Gingold2017-02-151-0/+59
* Add netlist generation infrastructure.Tristan Gingold2017-01-311-0/+126