| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth: add concatn gate | Tristan Gingold | 2019-07-19 | 1 | -0/+3 |
| * | synth: add const_z gate. | Tristan Gingold | 2019-07-19 | 1 | -0/+2 |
| * | synth: add Id_Port gate to improve display. | Tristan Gingold | 2019-07-10 | 1 | -23/+24 |
| * | netlists: add reduce_or/reduce_and gates. | Tristan Gingold | 2019-07-04 | 1 | -0/+2 |
| * | netlists: add assume gate. | Tristan Gingold | 2019-07-04 | 1 | -0/+1 |
| * | synth: handle concurrent assertions. | Tristan Gingold | 2019-07-02 | 1 | -0/+3 |
| * | synth: add dyn_insert module. | Tristan Gingold | 2019-07-01 | 1 | -4/+10 |
| * | synth: add ule, fix gate number. | Tristan Gingold | 2019-06-30 | 1 | -29/+29 |
| * | synth: disp_vhdl: handle mux2 | Tristan Gingold | 2019-06-28 | 1 | -0/+4 |
| * | synth: add get_input_net helper. | Tristan Gingold | 2019-06-28 | 1 | -1/+7 |
| * | synth: add syn_extract for dynamic slices. | Tristan Gingold | 2019-06-28 | 1 | -1/+2 |
| * | synth: add insert gate. | Tristan Gingold | 2019-06-24 | 1 | -0/+10 |
| * | synth: use only one edge gate, make it fully abstract. Handle falling_edge. | Tristan Gingold | 2019-05-22 | 1 | -5/+4 |
| * | synth: add comments. | Tristan Gingold | 2019-04-16 | 1 | -3/+13 |
| * | Add netlist generation infrastructure. | Tristan Gingold | 2017-01-31 | 1 | -0/+114 |
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index : iCE40/ghdl | |
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