iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth/elab-vhdl_values: add Value_Terminal	Tristan Gingold	2022-07-25	1	-0/+4
*	elab-vhdl_debug: disp fp64 values	Tristan Gingold	2022-07-20	1	-1/+2
*	elab-vhdl_values: add Create_Value_Quantity	Tristan Gingold	2022-07-16	1	-0/+4
*	synth: add value_dyn_alias in elab-vhdl_values	Tristan Gingold	2022-05-25	1	-0/+3
*	elab-vhdl_objtypes: use value_offsets for record elements offset.	Tristan Gingold	2022-05-24	1	-4/+4
*	elab-vhdl_values-debug: slightly improve output	Tristan Gingold	2022-05-24	1	-2/+6
*	synth: also use one-dimensional unbounded arrays for objtypes	Tristan Gingold	2022-05-22	1	-1/+14
*	synth: merge value for type_vector and type_array	Tristan Gingold	2022-05-22	1	-6/+6
*	elab-vhdl_values-debug: improve debug_typ output	Tristan Gingold	2022-05-22	1	-14/+37
*	synth: use unidimentional arrays in type_acc. Factorize code.	Tristan Gingold	2022-05-22	1	-29/+48
*	synth/elab-vhdl_values: use a proper type for signal_index	Tristan Gingold	2022-05-19	1	-1/+2
*	elab-vhdl_values-debug: add disp_type_short	Tristan Gingold	2022-05-15	1	-8/+55
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-0/+208