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author | Tristan Gingold <tgingold@free.fr> | 2022-05-19 06:43:47 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-05-19 06:43:47 +0200 |
commit | f8f24837237c8705c21b4b46c9f8474b50786f95 (patch) | |
tree | bd53681ee6d8e0b220773e2811734e74fab63c6e /src/synth/elab-vhdl_values-debug.adb | |
parent | ca53fab7cf13635747450b16525f5545c4b8bfe1 (diff) | |
download | ghdl-f8f24837237c8705c21b4b46c9f8474b50786f95.tar.gz ghdl-f8f24837237c8705c21b4b46c9f8474b50786f95.tar.bz2 ghdl-f8f24837237c8705c21b4b46c9f8474b50786f95.zip |
synth/elab-vhdl_values: use a proper type for signal_index
Diffstat (limited to 'src/synth/elab-vhdl_values-debug.adb')
-rw-r--r-- | src/synth/elab-vhdl_values-debug.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb index 193515e27..15da440e1 100644 --- a/src/synth/elab-vhdl_values-debug.adb +++ b/src/synth/elab-vhdl_values-debug.adb @@ -165,7 +165,8 @@ package body Elab.Vhdl_Values.Debug is case M.Typ.Kind is when Type_Bit | Type_Logic => - Put ("bit/logic"); + Put ("bit/logic: "); + Put_Uns32 (Uns32 (Read_U8 (M.Mem))); when Type_Vector => Put ("vector ("); Debug_Bound (M.Typ.Vbound, True); |