| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vhdl: preliminary work to elaborat quantities | Tristan Gingold | 2022-07-16 | 1 | -0/+2 |
| * | elab-vhdl_stmts: change parent of generate_body for for-generate | Tristan Gingold | 2022-05-14 | 1 | -1/+1 |
| * | synth: do full elaboration before synthesis | Tristan Gingold | 2021-11-01 | 1 | -0/+231 |
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index : iCE40/ghdl | |
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