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| author | Tristan Gingold <tgingold@free.fr> | 2022-07-16 08:31:51 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-07-16 08:31:51 +0200 |
| commit | 7c8ed1216609d69cd6a092620d7aa1334e432fd9 (patch) | |
| tree | 82ea5a780ef0d85183008401b45bb8ed881c3fb0 /src/synth/elab-vhdl_stmts.adb | |
| parent | ae7667c05858b9d7f6c1637a06497dfa138f635e (diff) | |
| download | ghdl-7c8ed1216609d69cd6a092620d7aa1334e432fd9.tar.gz ghdl-7c8ed1216609d69cd6a092620d7aa1334e432fd9.tar.bz2 ghdl-7c8ed1216609d69cd6a092620d7aa1334e432fd9.zip | |
vhdl: preliminary work to elaborat quantities
Diffstat (limited to 'src/synth/elab-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/elab-vhdl_stmts.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/elab-vhdl_stmts.adb b/src/synth/elab-vhdl_stmts.adb index 0deb80b5a..ce2648db0 100644 --- a/src/synth/elab-vhdl_stmts.adb +++ b/src/synth/elab-vhdl_stmts.adb @@ -185,6 +185,8 @@ package body Elab.Vhdl_Stmts is | Iir_Kind_Concurrent_Conditional_Signal_Assignment | Iir_Kind_Concurrent_Assertion_Statement | Iir_Kind_Concurrent_Procedure_Call_Statement + | Iir_Kind_Concurrent_Break_Statement + | Iir_Kind_Simple_Simultaneous_Statement | Iir_Kind_Psl_Default_Clock | Iir_Kind_Psl_Restrict_Directive | Iir_Kind_Psl_Assume_Directive |