iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	simul: use synth_declarations for processes and procedures	Tristan Gingold	2022-09-17	1	-13/+0
*	synth: factorize code (reuse synth_constant_declaration)	Tristan Gingold	2022-09-17	1	-64/+5
*	synth: handle incomplete types	Tristan Gingold	2022-09-17	1	-1/+11
*	synth: preliminary work to factorize code	Tristan Gingold	2022-09-16	1	-3/+1
*	synth: improve handling of top-level interfaces subtype	Tristan Gingold	2022-09-11	1	-0/+2
*	synth: fix and add checks for memory management.	Tristan Gingold	2022-09-10	1	-3/+1
*	simul: add support for protected objects	Tristan Gingold	2022-09-08	1	-7/+2
*	elab-vhdl_values: factorize code	Tristan Gingold	2022-09-07	1	-1/+1
*	synth: use areapools	Tristan Gingold	2022-09-02	1	-2/+45
*	elab: add default value to ports	Tristan Gingold	2022-08-23	1	-9/+16
*	elab-vhdl_expr: factorize code	Tristan Gingold	2022-08-19	1	-5/+10
*	simul: gather terminals	Tristan Gingold	2022-07-25	1	-0/+28
*	elab-vhdl_decls: elaborate dot attribute	Tristan Gingold	2022-07-21	1	-0/+13
*	vhdl-nodes: renaming.	Tristan Gingold	2022-07-21	1	-3/+3
*	elab-vhdl_decls: elaborate implicit signals	Tristan Gingold	2022-07-21	1	-2/+23
*	vhdl: preliminary work to elaborat quantities	Tristan Gingold	2022-07-16	1	-0/+13
*	elab-vhdl_types(Elab_Declaration_Type): rework to handle 'subtype	Tristan Gingold	2022-06-09	1	-8/+12
*	synth: handle suspend state declaration and statement	Tristan Gingold	2022-05-27	1	-0/+7
*	synth: add a flag to force creation of variables	Tristan Gingold	2022-05-11	1	-5/+13
*	synth: handle shared variable without default value.	Tristan Gingold	2022-04-04	1	-1/+1
*	synth: handle package instantiation in declarations. Fix #1938	Tristan Gingold	2022-01-03	1	-0/+3
*	synth: do full elaboration before synthesis	Tristan Gingold	2021-11-01	1	-0/+361