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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-16 19:55:00 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-16 19:55:00 +0200 |
| commit | 2a51f0c5c65d5d71c5abbd0631a0ec5660678520 (patch) | |
| tree | a3f077806dced3a7106bf990f589184fbde30d62 /src/synth/elab-vhdl_decls.adb | |
| parent | 7f411fd357bc9a17dc3d0593b86f4b8412a94632 (diff) | |
| download | ghdl-2a51f0c5c65d5d71c5abbd0631a0ec5660678520.tar.gz ghdl-2a51f0c5c65d5d71c5abbd0631a0ec5660678520.tar.bz2 ghdl-2a51f0c5c65d5d71c5abbd0631a0ec5660678520.zip | |
synth: preliminary work to factorize code
Diffstat (limited to 'src/synth/elab-vhdl_decls.adb')
| -rw-r--r-- | src/synth/elab-vhdl_decls.adb | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/synth/elab-vhdl_decls.adb b/src/synth/elab-vhdl_decls.adb index d7ceef8e5..5d5f38d25 100644 --- a/src/synth/elab-vhdl_decls.adb +++ b/src/synth/elab-vhdl_decls.adb @@ -295,7 +295,6 @@ package body Elab.Vhdl_Decls is Obj_Typ : Type_Acc; Base : Valtyp; Typ : Type_Acc; - Dyn : Dyn_Name; begin Mark_Expr_Pool (Marker); @@ -307,8 +306,7 @@ package body Elab.Vhdl_Decls is Obj_Typ := null; end if; - Synth_Assignment_Prefix (Syn_Inst, Get_Name (Decl), Base, Typ, Off, Dyn); - pragma Assert (Dyn = No_Dyn_Name); + Synth_Assignment_Prefix (Syn_Inst, Get_Name (Decl), Base, Typ, Off); Typ := Unshare (Typ, Instance_Pool); Res := Create_Value_Alias (Base, Off, Typ, Expr_Pool'Access); if Obj_Typ /= null then |