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path: root/src/synth/elab-vhdl_debug.adb
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* elab-vhdl_debug: add 'info lib' and 'info units'Tristan Gingold2023-01-211-0/+78
* elab-vhdl_debug: disp generate block declarationsTristan Gingold2023-01-201-2/+4
* elab-vhdl_debug: disp process declarationsTristan Gingold2023-01-201-0/+10
* elab-vhdl_debug: add option /t to print result typeTristan Gingold2023-01-141-5/+6
* synth: improve support of PSL endpointsTristan Gingold2023-01-111-1/+2
* simul: improve support of psl in debuggerTristan Gingold2023-01-111-0/+3
* elab-vhdl_debug: makes work and std visibleTristan Gingold2023-01-051-4/+17
* elab-vhdl_debug: avoid a crash on error in printTristan Gingold2023-01-041-5/+9
* elab-vhdl_debug: handle protected type body, nested packagesTristan Gingold2023-01-041-5/+11
* elab-vhdl_debug: add pheap command, improve access displayTristan Gingold2023-01-041-1/+32
* synth: introduce type_array_unboundedTristan Gingold2023-01-031-0/+3
* synth: add statement in context, adjust path/instance name attributesTristan Gingold2022-12-311-1/+3
* synth: add value_sig_val to handle individual signal associationsTristan Gingold2022-12-261-0/+2
* simul: improve debugger (display of signals value)Tristan Gingold2022-10-061-11/+39
* synth: rename vhdl.annotations to elab.vhdl_annotationsTristan Gingold2022-09-191-2/+2
* synth: use areapoolsTristan Gingold2022-09-021-4/+2
* synth: factorize code for tracing statements executionTristan Gingold2022-09-021-0/+12
* synth/elab-vhdl_values: add Value_TerminalTristan Gingold2022-07-251-0/+2
* elab-vhdl_debug: handle signals in packagesTristan Gingold2022-07-201-2/+8
* elab-vhdl_debug: disp fp64 valuesTristan Gingold2022-07-201-1/+1
* elab-vhdl_values: add Create_Value_QuantityTristan Gingold2022-07-161-0/+2
* elab-vhdl_debug: add print commandTristan Gingold2022-06-041-1/+296
* synth: handle suspend state declaration and statementTristan Gingold2022-05-271-0/+9
* elab-vhdl_debug: handle records in disp_memtyp.Tristan Gingold2022-05-271-4/+28
* synth: add value_dyn_alias in elab-vhdl_valuesTristan Gingold2022-05-251-0/+2
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-221-2/+2
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-221-9/+6
* synth/elab-vhdl_values: use a proper type for signal_indexTristan Gingold2022-05-191-1/+1
* elab-vhdl_debug(disp_instance_path): can also display componentsTristan Gingold2022-05-161-6/+20
* elab-vhdl_debug: factorize code, make Put_Dir publicTristan Gingold2022-05-161-12/+3
* elab-vhdl_debug: improve info signalsTristan Gingold2022-05-151-20/+19
* elab-vhdl_debug(disp_instance_path): show top-level unitTristan Gingold2022-05-151-13/+5
* ghdlsimul: add and improve debuggerTristan Gingold2022-05-141-23/+322
* elab-vhdl_debug: also disp declarations in instancesTristan Gingold2022-05-121-4/+1
* elab-vhdl_debug: also print objects in disp_hierarchyTristan Gingold2022-05-011-55/+137
* synth: extract elab-vhdl_debug from elab-debuggerTristan Gingold2022-04-291-0/+629
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