iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	simul: fix handling of drivers/sensitivity within processes	Tristan Gingold	2023-01-12	1	-10/+1
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*	simul: fix signal attribute or guard as actual in connections	Tristan Gingold	2022-10-06	1	-1/+3
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*	simul: factorize code, add sub_signal_type	Tristan Gingold	2022-09-29	1	-10/+6
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*	simul: gather disconnection specifications, create guard signal	Tristan Gingold	2022-09-25	1	-0/+17
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*	simul: handle more signals types	Tristan Gingold	2022-09-15	1	-0/+3
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*	simul: factorize code to compute number of sources	Tristan Gingold	2022-08-23	1	-0/+9
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*	simul: add extra drivers for ports without sources	Tristan Gingold	2022-08-23	1	-0/+11
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*	simul: handle resolved signals (WIP)	Tristan Gingold	2022-08-19	1	-1/+2
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*	simul: add create_connects	Tristan Gingold	2022-08-17	1	-6/+12
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*	simul: create terminals (WIP)	Tristan Gingold	2022-08-17	1	-0/+10
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*	simul: gather terminals	Tristan Gingold	2022-07-25	1	-0/+14
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*	src/simul: rewrite of ghdl/simul based on synth	Tristan Gingold	2022-07-24	1	-0/+200