| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | simul-vhdl_debug: display connections | Tristan Gingold | 2022-08-19 | 1 | -5/+63 |
| * | simul: add create_connects | Tristan Gingold | 2022-08-17 | 1 | -2/+2 |
| * | simul-vhdl_debug: add info terminal | Tristan Gingold | 2022-07-28 | 1 | -20/+69 |
| * | src/simul: rewrite of ghdl/simul based on synth | Tristan Gingold | 2022-07-24 | 1 | -0/+728 |
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index : iCE40/ghdl | |
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