iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	psl-nfa-utils: move active state in merge_state.	Tristan Gingold	2019-10-31	1	-0/+5
*	psl: add active state.	Tristan Gingold	2019-10-21	4	-20/+71
*	psl-nfas-utils: reuse True_Node.	Tristan Gingold	2019-10-21	1	-4/+2
*	vhdl: Add the implicit [*] at start of PSL cover sequence.	Tristan Gingold	2019-10-15	2	-0/+30
*	fix: move src/xtools to python/xtools (#846)	1138-4EB	2019-06-17	1	-1/+1
*	vhdl-prints: handle PSL, add psl tokens for strong and inclusive variants.	Tristan Gingold	2019-05-30	1	-0/+2
*	vhdl: renames disp_vhdl to prints	Tristan Gingold	2019-05-30	2	-0/+2
*	vhdl-disp_vhdl: fixes for psl.	Tristan Gingold	2019-05-25	1	-2/+16
*	psl: can keep parenthesis during parse.	Tristan Gingold	2019-05-24	5	-32/+74
*	errorout: add messages group instead of continuation.	Tristan Gingold	2019-05-12	1	-1/+1
*	vhdl: decouple errorouts a bit more.	Tristan Gingold	2019-05-10	2	-1/+14
*	psl: add psl-types, psl-nodes_priv.	Tristan Gingold	2019-05-10	15	-3/+72
*	Extract psl-errors from errorout.	Tristan Gingold	2019-05-10	2	-0/+64
*	psl-rewrites: handle and/or seq.	Tristan Gingold	2018-11-30	1	-1/+3
*	psl: adjust after pnodes.py changes and regenerate.	Tristan Gingold	2017-10-28	2	-12/+12
*	PSL: add clocked SERE, make endpoints visible from VHDL.	Tristan Gingold	2016-03-22	6	-20/+48
*	wip.	Tristan Gingold	2016-03-20	1	-2/+3
*	psl: cover directive works on a sequence, not on a property.	Tristan Gingold	2016-02-14	4	-8/+15
*	Improve mixed dump of PSL and VHDL nodes.	Tristan Gingold	2016-02-09	2	-18/+8
*	psl: use Tables instead of GNAT.Table, regenerate, add copyrights.	Tristan Gingold	2016-01-27	31	-59/+609
*	Add missing psl files.	Tristan Gingold	2015-05-10	5	-0/+2008
*	psl: add generated files.	Tristan Gingold	2015-05-10	3	-1555/+750
*	Regenerate psl-dump_tree.adb. Fix build failure (ticket 42).	Tristan Gingold	2015-05-10	1	-180/+68
*	Move sources to src/ subdirectory.	Tristan Gingold	2014-11-04	30	-0/+7521