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* ams-vhdl: analyze, canon and print simultaneous procedural statements.Tristan Gingold2019-12-306-90/+175
* ams-vhdl: fix tree consistency for terminal declaration.Tristan Gingold2019-12-302-3/+3
* testsuite/vets/vhdl-ams: fix syntax.Tristan Gingold2019-12-3014-42/+42
* ams-vhdl: correctly test and set staticness of dot/integ attributes.Tristan Gingold2019-12-301-8/+7
* ams-vhdl: print subnature declarations.Tristan Gingold2019-12-301-1/+16
* ams-vhdl: check nature for record natures and terminals.Tristan Gingold2019-12-309-466/+646
* vhdl-ams: fix tree consistency for subnature declaration.Tristan Gingold2019-12-294-9/+9
* vhdl-ams: fix overload for simple simultaneous statement.Tristan Gingold2019-12-293-4/+26
* testsuite/synth: add test for #1058Tristan Gingold2019-12-293-0/+61
* synth: handle wire assigned to a static value. Fix #1058Tristan Gingold2019-12-293-9/+104
* testsuite/vests: add files-ams.txtTristan Gingold2019-12-282-0/+730
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-2839-1800/+6981
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-268-106/+186
* vhdl-prints: subtype indication is optional in object alias.Tristan Gingold2019-12-261-3/+2
* testsuite: add a test for previous changeTristan Gingold2019-12-263-0/+28
* libraries: handle redefinition of a package by an entity.Tristan Gingold2019-12-261-75/+80
* testsuite/gna: add a test for #1057Tristan Gingold2019-12-243-0/+22
* vhdl: handle non-object aliases in selected use clause. Fix #1057Tristan Gingold2019-12-241-5/+8
* testsuite/synth: add testcase for #1054Tristan Gingold2019-12-243-0/+66
* synth: handle is_x (as false). Fix #1054Tristan Gingold2019-12-241-0/+4
* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-246-353/+367
* testsuite/synth: add test for #1021Tristan Gingold2019-12-244-0/+217
* ghdlsynth: allow display for libghdl.Tristan Gingold2019-12-241-21/+42
* netlists-disp_vhdl: handle conversion from std_logic to signed/unsigned.Tristan Gingold2019-12-242-8/+20
* netlists-memories: add convert_to_memory.Tristan Gingold2019-12-241-298/+504
* synth: add minor comments.Tristan Gingold2019-12-232-1/+3
* synth: add Get_Input_Instance.Tristan Gingold2019-12-144-10/+21
* netlists-memories: add comments.Tristan Gingold2019-12-141-2/+44
* netlists-memories: remove unused subprograms.Tristan Gingold2019-12-081-318/+0
* netlists-memories: reduce muxes.Tristan Gingold2019-12-081-1/+162
* synth: rework in netlists-memories.Tristan Gingold2019-12-061-61/+128
* libraries/ieee2008: partial merge of vhdl2019 for fixed_generic_pkgTristan Gingold2019-12-061-373/+363
* testsuite: add a test for #1018Tristan Gingold2019-12-052-0/+36
* netlists-disp_vhdl: handle 1-bit add/sub.Tristan Gingold2019-12-051-4/+12
* netlists-memories: avoid a crash when no read. Fix #1018Tristan Gingold2019-12-051-1/+7
* netlists-disp_vhdl: handle more ROMs.Tristan Gingold2019-12-051-2/+12
* netlists-memories: improve ROM inference. For issue #1008Tristan Gingold2019-12-051-26/+48
* netlists-dump: adjust can_inline after cleanup ofTristan Gingold2019-12-051-4/+20
* netlists-memories: generate mem_rd_sync gates.Tristan Gingold2019-12-052-170/+142
* netlists-gates: add comments.Tristan Gingold2019-12-051-3/+13
* netlists-disp_vhdl: handle id_mem_rd_syncTristan Gingold2019-12-051-0/+15
* netlists: add enable port to id_mem_rd_sync.Tristan Gingold2019-12-052-10/+20
* netlists: add remove_output_gates.Tristan Gingold2019-12-053-0/+31
* netlists-memories: rework.Tristan Gingold2019-12-053-3/+857
* synth: add set_location_maybe (for roms).Tristan Gingold2019-12-053-2/+35
* ghdlsynth: fix crash on synthesis of a second design.Tristan Gingold2019-12-051-0/+4
* testsuite: add test for #1050Tristan Gingold2019-12-042-0/+47
* netlists-disp_vhdl: handle unconnected outputs. Fix #1050Tristan Gingold2019-12-041-10/+10
* testsuite: add test for #1007Tristan Gingold2019-12-033-0/+59
* synth: create unique instance name. Fix #1007Tristan Gingold2019-12-032-4/+155
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